Angelo Nagari

According to our database1, Angelo Nagari authored at least 22 papers between 1996 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
A ΣΔ sense chain using chopped integrators for ultra-low-noise MEMS system.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time ΣΔ ADC for a Digital Closed-Loop Class-D Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Introduction to the Special Issue on the 40th European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits, 2015

An FSK modulator at 23.2 MHz with ±0.9% accuracy for the USB power delivery standard.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
A fully integrated Class-D amplifier in 40nm CMOS with dynamic cascode bias and load current sensing.
Proceedings of the ESSCIRC 2014, 2014

2013
A 40-nm CMOS, 1.1-V, 101-dB DR, 1.7-mW continuous-time ΣΔ ADC for a digital closed-loop class-D amplifier.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
An 8 Ω 2.5 W 1%-THD 104 dB(A)-Dynamic-Range Class-D Audio Amplifier With Ultra-Low EMI System and Current Sensing for Speaker Protection.
IEEE J. Solid State Circuits, 2012

A 65-nm, 1-A Buck Converter With Multi-Function SAR-ADC-Based CCM/PSK Digital Control Loop.
IEEE J. Solid State Circuits, 2012

An 8Ω 2.5W 1%-THD 104dB(A)-dynamic-range Class-D audio amplifier with an ultra-low EMI system and current sensing for speaker protection.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A synchronized self oscillating Class-D amplifier for mobile application.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
Conducted EMI prediction for integrated class D audio amplifier.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Analysis and design of an analog control loop for digital input class D amplifiers.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2009
A 0.01%THD, 70dB PSRR Single Ended Class D using Variable Hysteresis Control for Headphone Amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A topological comparison of PWM and hysteresis controls in switching audio amplifiers.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2004
A 2.7mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

A 2.7V 350muW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs.
Proceedings of the 2004 Design, 2004

2000
A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSM applications.
IEEE J. Solid State Circuits, 2000

1998
A high-performance analog front-end 14-bit codec for 2.7-V digital cellular phones.
IEEE J. Solid State Circuits, 1998

A 3 V 10 MHz pseudo-differential SC bandpass filter using gain enhancement replica amplifier.
IEEE J. Solid State Circuits, 1998

1997
Low-voltage double-sampled ΣΔ converters.
IEEE J. Solid State Circuits, 1997

A 10.7-MHz BiCMOS high-Q double-sampled SC bandpass filter.
IEEE J. Solid State Circuits, 1997

1996
A -80 dB THD, 4 V<sub>pp</sub> switched capacitor filter for 1.5 V battery-operated systems.
IEEE J. Solid State Circuits, 1996


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