Marian Verhelst

Orcid: 0000-0003-3495-9263

According to our database1, Marian Verhelst authored at least 209 papers between 2004 and 2024.

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Bibliography

2024
Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

TreeGRNG: Binary Tree Gaussian Random Number Generator for Efficient Probabilistic AI Hardware.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024


2023
An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing.
IEEE J. Solid State Circuits, November, 2023

An End-to-End Dual ASIC OFDM Transceiver for Ultrasound In-Body Communication.
IEEE Trans. Biomed. Circuits Syst., August, 2023

DepFiN: A 12-nm Depth-First, High-Resolution CNN Processor for IO-Efficient Inference.
IEEE J. Solid State Circuits, May, 2023

A 96-Channel 40nm CMOS Potentiostat for Parallel Experiments on Microbial Electrochemical Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2023

CNN-based Robust Sound Source Localization with SRP-PHAT for the Extreme Edge.
ACM Trans. Embed. Comput. Syst., 2023

TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge.
IEEE J. Solid State Circuits, 2023

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge.
IEEE J. Solid State Circuits, 2023

Benchmarking and modeling of analog and digital SRAM in-memory computing architectures.
CoRR, 2023

NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking.
CoRR, 2023

A 384-Channel Online-Spike-Sorting IC Using Unsupervised Geo-OSort Clustering and Achieving 0.0013mm<sup>2</sup>/Ch and $1.78\mu \text{W/ch}$.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Stream: A Modeling Framework for Fine-grained Layer Fusion on Multi-core DNN Accelerators.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Precision-aware Latency and Energy Balancing on Multi-Accelerator Platforms for DNN Inference.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023

ACCO: Automated Causal CNN Scheduling Optimizer for Real-Time Edge Accelerators.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

Analog or Digital In-Memory Computing? Benchmarking Through Quantitative Modeling.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm<sup>2</sup>, 256kB/mm<sup>2</sup> and 23. 8TOPs/W.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

Real-Time Acoustic Perception for Automotive Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Genetic Algorithm-based Framework for Layer-Fused Scheduling of Multiple DNNs on Multi-core Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023


PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Hardware-aware NAS by Genetic Optimisation with a Design Space Exploration Simulator.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
GraphOpt: Constrained-Optimization-Based Parallelization of Irregular Graphs.
IEEE Trans. Parallel Distributed Syst., 2022

Taxonomy and Benchmarking of Precision-Scalable MAC Arrays Under Enhanced DNN Dataflow Representation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm.
IEEE J. Solid State Circuits, 2022

Enabling real-time object detection on low cost FPGAs.
J. Real Time Image Process., 2022

Fair and Comprehensive Benchmarking of Machine Learning Processing Chips.
IEEE Des. Test, 2022

Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks.
CoRR, 2022

CONVOLVE: Smart and seamless design of smart edge processors.
CoRR, 2022

Hardware-aware mobile building block evaluation for computer vision.
CoRR, 2022

Delta Keyword Transformer: Bringing Transformers to the Edge through Dynamically Pruned Multi-Head Self-Attention.
CoRR, 2022

TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

DPU-v2: Energy-efficient execution of irregular directed acyclic graphs.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Learn to Learn on Chip: Hardware-aware Meta-learning for Quantized Few-shot Learning at the Edge.
Proceedings of the 7th IEEE/ACM Symposium on Edge Computing, 2022

Discrete Samplers for Approximate Inference in Probabilistic Machine Learning.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A Flexible End-to-End Dual ASIC Transceiver for OFDM Ultrasound In-Body Communication.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

Optimizing Accelerator Configurability for Mobile Transformer Networks.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting.
IEEE Trans. Very Large Scale Integr. Syst., 2021

High-Utilization, High-Flexibility Depth-First CNN Coprocessor for Image Pixel Processing on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Hardware Acceleration for Embedded Keyword Spotting: Tutorial and Survey.
ACM Trans. Embed. Comput. Syst., 2021

A Scalable 128-Channel, Time-Multiplexed Potentiostat for Parallel Electrochemical Experiments.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators.
IEEE Trans. Computers, 2021

Hardware-Efficient Residual Neural Network Execution in Line-Buffer Depth-First Processing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Performance analysis of in-band collision detection for dense wireless networks.
EURASIP J. Wirel. Commun. Netw., 2021

DPU: DAG Processing Unit for Irregular Graphs with Precision-Scalable Posit Arithmetic in 28nm.
CoRR, 2021

Survey and Benchmarking of Precision-Scalable MAC Arrays for Embedded DNN Processing.
CoRR, 2021

DepFiN: A 12nm, 3.8TOPs depth-first CNN processor for high res. image processing.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Processor Architecture Optimization for Spatially Dynamic Neural Networks.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

9.4 PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

PeakRNN and StatsRNN: Dynamic Pruning in Recurrent Neural Networks.
Proceedings of the 29th European Signal Processing Conference, 2021

A 96-channel 40nm CMOS Fully-Integrated Potentiostat for Electrochemical Monitoring.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
Binary CorNET: Accelerator for HR Estimation From Wrist-PPG.
IEEE Trans. Biomed. Circuits Syst., 2020

On the Convexity of Bit Depth Allocation for Linear MMSE Estimation in Wireless Sensor Networks.
IEEE Signal Process. Lett., 2020

Distributed adaptive node-specific signal estimation in a wireless sensor network with noisy links.
Signal Process., 2020

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS.
IEEE J. Solid State Circuits, 2020

Vocell: A 65-nm Speech-Triggered Wake-Up SoC for 10- $\mu$ W Keyword Spotting and Speaker Verification.
IEEE J. Solid State Circuits, 2020

ZigZag: A Memory-Centric Rapid DNN Accelerator Design Space Exploration Framework.
CoRR, 2020

Benchmarking TinyML Systems: Challenges and Direction.
CoRR, 2020

Dynamic Complexity Tuning for Hardware-Aware Probabilistic Circuits.
Proceedings of the IoT Streams for Data-Driven Predictive Maintenance and IoT, Edge, and Mobile for Embedded Machine Learning, 2020

Discriminative Bias for Learning Probabilistic Sentential Decision Diagrams.
Proceedings of the Advances in Intelligent Data Analysis XVIII, 2020

An Affordable Multichannel Potentiostat with 128 Individual Stimulation and Sensing Channels.
Proceedings of the 2020 IEEE International Instrumentation and Measurement Technology Conference, 2020

Feed-Forward On-Edge Fine-Tuning Using Static Synthetic Gradient Modules.
Proceedings of the Computer Vision - ECCV 2020 Workshops, 2020

Acceleration of probabilistic reasoning through custom processor architecture.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Current-Driven Six-Channel Potentiostat for Rapid Performance Characterization of Microbial Electrolysis Cells.
IEEE Trans. Instrum. Meas., 2019

Enabling Ultrasound In-Body Communication: FIR Channel Models and QAM Experiments.
IEEE Trans. Biomed. Circuits Syst., 2019

An Always-On 3.8 $\mu$ J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019

Breaking High-Resolution CNN Bandwidth Barriers With Enhanced Depth-First Execution.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

18μW SoC for near-microphone Keyword Spotting and Speaker Verification.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Towards Hardware-Aware Tractable Learning of Probabilistic Models.
Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019

On Hardware-Aware Probabilistic Frameworks for Resource Constrained Embedded Applications.
Proceedings of the Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing, 2019

A 978GOPS/W Flexible Streaming Processor for Real-Time Image Processing Applications in 22nm FDSOI.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 64-channel, 1.1-pA-accurate On-chip Potentiostat for Parallel Electrochemical Monitoring.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

Exploration and Design of Low-Energy Logic Cells for 1 kHz Always-on Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

ProbLP: A framework for low-precision probabilistic inference.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Wearable Wrist-Band with Compressive Sensing based Ultra-Low Power Photoplethysmography Readout Circuit.
Proceedings of the 16th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2019

Real-time HR Estimation from wrist PPG using Binary LSTMs.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

Ultrasound In-Body Communication with OFDM through Multipath Realistic Channels.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

Efficient Keyword Spotting through Hardware-Aware Conditional Execution of Deep Neural Networks.
Proceedings of the 16th IEEE/ACS International Conference on Computer Systems and Applications, 2019

Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

Survey of Precision-Scalable Multiply-Accumulate Units for Neural-Network Processing.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
Energy-Efficient Digital Front-End Processor for 60 GHz Polar Transmitter.
J. Signal Process. Syst., 2018

A Fully Configurable Non-Linear Mixed-Signal Interface for Multi-Sensor Analytics.
IEEE J. Solid State Circuits, 2018

Dynamic Sensor-Frontend Tuning for Resource Efficient Embedded Classification.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Optimized Hierarchical Cascaded Processing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

A multi-layered energy consumption model for smart wireless acoustic sensor networks.
CoRR, 2018

Resource aware design of a deep convolutional-recurrent neural network for speech recognition through audio-visual sensor fusion.
CoRR, 2018

A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Towards Resource-Efficient Classifiers for Always-On Monitoring.
Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2018

Efficiently Combining SVD, Pruning, Clustering and Retraining for Enhanced Neural Network Compression.
Proceedings of the 2nd International Workshop on Embedded and Mobile Deep Learning, 2018

On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs.
Proceedings of the IEEE International Test Conference, 2018

An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Mixed-signal programmable non-linear interface for resource-efficient multi-sensor analytics.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Bit Error Tolerance of a CIFAR-10 Binarized Convolutional Neural Network Processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

From on-chip self-healing to self-adaptivity in analog/RF ICs: challenges and opportunities.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Evolving hardware instinctive behaviors in resource-scarce agent swarms exploring hard-to-reach environments.
Proceedings of the Genetic and Evolutionary Computation Conference Companion, 2018

Exploiting FDSOI towards minimum energy point operation in processors and machine learning accelerators.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

Flexible and Self-Adaptive Sense-and-Compress for Sub-MicroWatt Always-on Sensory Recording.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

Laika: A 5uW Programmable LSTM Accelerator for Always-on Keyword Spotting in 65nm CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

Feature noise tuning for resource efficient Bayesian Network Classifiers.
Proceedings of the 26th European Symposium on Artificial Neural Networks, 2018

TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs.
Proceedings of the 55th Annual Design Automation Conference, 2018

BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
Adaptive Quantization for Multichannel Wiener Filter-Based Speech Enhancement in Wireless Acoustic Sensor Networks.
Wirel. Commun. Mob. Comput., 2017

Split-Delta Background Calibration for SAR ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 172 µW Compressively Sampled Photoplethysmographic (PPG) Readout ASIC With Heart Rate Estimation Directly From Compressively Sampled Data.
IEEE Trans. Biomed. Circuits Syst., 2017

An Energy-Efficient Precision-Scalable ConvNet Processor in 40-nm CMOS.
IEEE J. Solid State Circuits, 2017

Multidisciplinary Learning through Implementation of the DVB-S2 Standard.
IEEE Commun. Mag., 2017

An 8-11b 320kS/s resolution scalable noise shaping SAR ADC.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Successive parabolic interpolation as extremum seeking control for microbial fuel & electrolysis cells.
Proceedings of the IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, China, October 29, 2017

Instinct-driven dynamic hardware reconfiguration: evolutionary algorithm optimized compression for autonomous sensory agents.
Proceedings of the Genetic and Evolutionary Computation Conference, 2017

The SINS Database for Detection of Daily Activities in a Home Environment Using an Acoustic Sensor Network.
Proceedings of the Workshop on Detection and Classification of Acoustic Scenes and Events, 2017

DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Exploring the unknown through successive generations of low power and low resource versatile agents.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Impact of interference correlation on the decoding error statistics.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

Minimum energy quantized neural networks.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

Optimal Tiling Strategy for Memory Bandwidth Reduction for CNNs.
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2017

2016
Optimizing the Code Rate of Energy-Constrained Wireless Communications With HARQ.
IEEE Trans. Wirel. Commun., 2016

Finite-Horizon Prediction of Energy Depletions in Off-Grid Wireless Networks.
IEEE Trans. Veh. Technol., 2016

Generalized Signal Utility for LMMSE Signal Estimation With Application to Greedy Quantization in Wireless Sensor Networks.
IEEE Signal Process. Lett., 2016

A 90 nm CMOS, 6µW Power-Proportional Acoustic Sensing Frontend for Voice Activity Detection.
IEEE J. Solid State Circuits, 2016

Understanding Interdependency Through Complex Information Sharing.
Entropy, 2016

Energy-efficient ConvNets through approximate computing.
Proceedings of the 2016 IEEE Winter Conference on Applications of Computer Vision, 2016

A 0.3-2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

22.4 A 172µW compressive sampling photoplethysmographic readout with embedded direct heart-rate and variability extraction from compressively sampled data.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Session 14 overview: Next-generation processing.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

F1: Designing secure systems: Manufacturing, circuits and architectures.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A switched-capacitor degenerated, scalable gm-C filter-bank for acoustic front-ends.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Extending Naive Bayes with Precision-tunable Feature Variables for Resource-efficient Sensor Fusion.
Proceedings of the 2nd Workshop on Artificial Intelligence and Internet of Things co-located with the 22nd European Conference on Artificial Intelligence (ECAI 2016), 2016

Custom processor design for efficient, yet flexible Lucas-Kanade optical flow.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

PHIDIAS: ultra-low-power holistic design for smart bio-signals computing platforms.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Performance analysis of in-band full duplex collision and interference detection in dense networks.
Proceedings of the 13th IEEE Annual Consumer Communications & Networking Conference, 2016

A 17nA, 47.2dB dynamic range, adaptive sampling controller for online data rate reduction in low power ECG systems.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

Exploiting system configurability towards dynamic accuracy-power trade-offs in sensor front-ends.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

2015
Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers.
J. Signal Process. Syst., 2015

Built-In Self-Test of Transmitter I/Q Mismatch and Nonlinearity Using Self-Mixing Envelope Detector.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Efficient Timing Mismatch Correction for Low-Cost Digital-Mixing Transmitter.
IEEE Trans. Signal Process., 2015

On the General Mathematical Framework, Calibration/Compensation Method, and Applications of Non-Ideal Software Defined Harmonics Rejection Transceivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Introduction to the Special Issue on the 40th European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits, 2015

A mm-Precise 60 GHz Transmitter in 40 nm CMOS for Discrete-Carrier Indoor Localization.
IEEE J. Solid State Circuits, 2015

Optimal resource usage in ultra-low-power sensor interfaces through context- and resource-cost-aware machine learning.
Neurocomputing, 2015

Energy-efficient MIMO multihop communications using the antenna selection scheme.
Proceedings of the 2015 International Symposium on Wireless Communication Systems (ISWCS), 2015

F4: Building the Internet of Everything (IoE): Low-power techniques at the circuit and system levels.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

24.2 Context-aware hierarchical information-sensing in a 6μW 90nm CMOS voice activity detector.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

DVAS: Dynamic Voltage Accuracy Scaling for increased energy-efficiency in approximate computing.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Redundancy effect on the performance of digitally-assisted SAR ADCs.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

<30 mW rectangular-to-polar conversion processor in 802.11ad polar transmitter.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

Energy-vs-performance trade-offs in speech enhancement in wireless acoustic sensor networks.
Proceedings of the 23rd European Signal Processing Conference, 2015

An energy-scalable in-band full duplex architecture.
Proceedings of the 20th IEEE International Workshop on Computer Aided Modelling and Design of Communication Links and Networks, 2015

Using mobility for increasing the energy efficiency of multihop communications.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
Energy-Efficiency and Accuracy of Stochastic Computing Circuits in Emerging Technologies.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

CLAWS: Cross-Layer Adaptable Wireless System enabling full cross-layer experimentation on real-time software-defined 802.15.4.
EURASIP J. Wirel. Commun. Netw., 2014

Impact of multipath fading on a precise 60 GHz indoor locationing system.
Proceedings of the 2014 22nd Signal Processing and Communications Applications Conference (SIU), 2014

Energy and accuracy in multi-stage stochastic computing.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Ultra-low-power voice-activity-detector through context- and resource-cost-aware feature selection in decision trees.
Proceedings of the IEEE International Workshop on Machine Learning for Signal Processing, 2014

20.1 A 40nm CMOS receiver for 60GHz discrete-carrier indoor localization achieving mm-precision at 4m range.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Efficient duty-cycle mismatch compensation in digital transmitter.
Proceedings of the IEEE International Conference on Acoustics, 2014

Design and implementation of a multi-standard event-driven energy management system for smart buildings.
Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

A 128∶2048/1536 point FFT hardware implementation with output pruning.
Proceedings of the 22nd European Signal Processing Conference, 2014

A 60GHz transmitter in 40nm CMOS achieving mm-precision for discrete-carrier localization.
Proceedings of the ESSCIRC 2014, 2014

Context- and cost-aware feature selection in ultra-low-power sensor interfaces.
Proceedings of the 22th European Symposium on Artificial Neural Networks, 2014

Computationally-efficient compressive sampling for low-power pulseoximeter system.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver.
IEEE J. Solid State Circuits, 2013

A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver.
IEEE J. Solid State Circuits, 2013

Efficient self-correction scheme for static non-idealities in nano-scale quadrature digital RF transmitters.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

A method for using sub-Nyquist sampling for ultra low-power positioning systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Flexible, ultra-low power sensor nodes through configurable finite state machines.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Adaptive filter based low complexity digital intensive harmonic rejection for SDR receiver.
Proceedings of the IEEE International Conference on Acoustics, 2013

2012
A Power-Scalable Channel-Adaptive Wireless Receiver Based on Built-In Orthogonally Tunable LNA.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Test Signal Development and Analysis for OFDM Systems RF Front-End Parameter Extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS.
IEEE J. Solid State Circuits, 2012

Built-in-Self Test of transmitter I/Q mismatch using self-mixing envelope detector.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

A Generic Framework for Optimizing Digital Intensive Harmonic Rejection Receivers.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Reduced Complexity On-chip IQ-Imbalance Self-Calibration.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Towards a Fast and Hardware Efficient Sub-MM Precision Ranging System.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012


A programmable calibration/BIST engine for RF/analog blocks in SoCs.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
Systematic Analysis of Interleaved Digital-to-Analog Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Power Consumption Minimization for MIMO Systems - A Cognitive Radio Approach.
IEEE J. Sel. Areas Commun., 2011

Orthogonally tunable inductorless RF LNA for adaptive wireless systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Extraction of EVM from Transmitter System Parameters.
Proceedings of the 16th European Test Symposium, 2011

2010
A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging.
IEEE J. Solid State Circuits, 2010

2009
A reconfigurable, 0.13µm CMOS 110pJ/pulse, fully integrated IR-UWB receiver for communication and sub-cm ranging.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

RFID, where are they?
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
Analysis of the QAC IR-UWB Receiver for Low Energy, Low Data-Rate Communication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A Flexible, Ultra-Low-Energy 35 pJ/Pulse Digital Back-End for a QAC IR-UWB Receiver.
IEEE J. Solid State Circuits, 2008

A low-power mixing DAC IR-UWB-receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A Low Power, Reconfigurable IR-UWB System.
Proceedings of IEEE International Conference on Communications, 2008

2007
A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication.
IEEE J. Solid State Circuits, 2007

A flexible, ultra-low power 35pJ/pulse digital back-end for a QAC UWB receiver.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2005
System design of an ultra-low power, low data rate, pulsed UWB receiver in the 0-960 MHz band.
Proceedings of IEEE International Conference on Communications, 2005

2004
Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004


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