Anil Kumar Rajput
Orcid: 0000-0002-3876-5514
According to our database1,
Anil Kumar Rajput
authored at least 8 papers
between 2016 and 2023.
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Bibliography
2023
An Energy-Efficient Hybrid SRAM-Based In-Memory Computing Macro for Artificial Intelligence Edge Devices.
Circuits Syst. Signal Process., June, 2023
Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation.
Microelectron. J., 2023
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
2022
Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture.
Microelectron. J., 2022
2020
Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond Von-Neumann Computation.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
2019
Network on Chip for Consumer Electronics Devices: An Architectural and Performance Exploration of Synchronous and Asynchronous Network-on-Chip-Based Systems.
IEEE Consumer Electron. Mag., 2019
Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
2016
Parametric Performance Analysis of Synchronous and Asynchronous Heterogeneous Network on Chip.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016