Manisha Pattanaik
According to our database1,
Manisha Pattanaik
authored at least 60 papers
between 2003 and 2023.
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Bibliography
2023
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model.
J. Electron. Test., August, 2023
An Energy-Efficient Hybrid SRAM-Based In-Memory Computing Macro for Artificial Intelligence Edge Devices.
Circuits Syst. Signal Process., June, 2023
Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation.
Microelectron. J., 2023
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
2022
A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems.
J. Electron. Test., December, 2022
J. King Saud Univ. Comput. Inf. Sci., November, 2022
Energy efficient logarithmic-based approximate divider for ASIC and FPGA-based implementations.
Microprocess. Microsystems, April, 2022
Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture.
Microelectron. J., 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Integr., 2021
READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency.
Integr., 2021
A Few Shot Learning based Approach for Hardware Trojan Detection using Deep Siamese CNN.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
2020
Bit significance based reconfigurable approximate restoring dividers and square rooters.
Microelectron. J., 2020
IET Circuits Devices Syst., 2020
Area and Energy Efficient Approximate Square Rooters for Error Resilient Applications.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond Von-Neumann Computation.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
2019
Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Proceedings of the 10th International Conference on Computing, 2019
2018
A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design.
Circuits Syst. Signal Process., 2018
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
2017
An Aging-Aware Reliable FinFET-Based Low-Power 32-Word \(\times \) 32-bit Register File.
Circuits Syst. Signal Process., 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
2016
J. Circuits Syst. Comput., 2016
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
2015
A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM.
Microelectron. Reliab., 2015
New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET.
J. Low Power Electron., 2015
J. Low Power Electron., 2015
J. Circuits Syst. Comput., 2015
Performance study of side block oxide band gap engineered SONOS: A device simulation approach.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
2014
Wirel. Pers. Commun., 2014
Edge preservation of impulse noise filtered images by improved anisotropic diffusion.
Multim. Tools Appl., 2014
Microelectron. Reliab., 2014
Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode.
Microelectron. J., 2014
Process, Voltage and Temperature Variations Aware Low Leakage Approach for Nanoscale CMOS Circuits.
J. Low Power Electron., 2014
J. Circuits Syst. Comput., 2014
Operation-aware assist circuit design for improved write performance of FinFET based SRAM.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
2013
Histogram statistics based variance controlled adaptive threshold in anisotropic diffusion for low contrast image enhancement.
Signal Process., 2013
Double-gate FinFET process variation aware 10T SRAM cell topology design and analysis.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders.
Proceedings of the International Symposium on Electronic System Design, 2012
A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate.
Proceedings of the International Symposium on Electronic System Design, 2012
A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM Cell.
Proceedings of the International Symposium on Electronic System Design, 2012
Fuzzy based diffusion coefficient function in anisotropic diffusion for impulse noise removal.
Proceedings of the Eighth Indian Conference on Vision, Graphics and Image Processing, 2012
2011
Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications.
VLSI Design, 2011
Circuits Syst., 2011
Stability and Leakage Analysis of a Novel PP Based 9T SRAM Cell Using N Curve at Deep Submicron Technology for Multimedia Applications.
Circuits Syst., 2011
Proceedings of the International Conference on Soft Computing for Problem Solving (SocProS 2011) December 20-22, 2011, 2011
An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique.
Proceedings of the International Symposium on Electronic System Design, 2011
2010
Proceedings of the IEEE International Conference on Systems, 2010
Performance analysis of dynamic threshold MOS (DTMOS) based 4-input multiplexer switch for low power and high speed FPGA design.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
An Efficient Compressed Domain Spatial Transcoding Scheme for Adaptive Video Content Delivery.
Proceedings of the Advances in Multimedia Information Processing - PCM 2010, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
2003
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003