Antonis Tsigkanos

According to our database, Antonis Tsigkanos authored at least 9 papers between 2015 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology.

Panagiotis Chatziantoniou, Antonis Tsigkanos, Dimitris Theodoropoulos, Nektarios Kranitis, Antonis M. Paschalis

IEEE Trans. Aerosp. Electron. Syst., 2022

High-Performance Hardware Accelerators for Next Generation On-Board Data Processing.

Antonis M. Paschalis, Panagiotis Chatziantoniou, Dimitris Theodoropoulos, Antonis Tsigkanos, Nektarios Kranitis

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2021

Σχεδίαση, υλοποίηση και ενσωμάτωση σε σύστημα-σε-μια-ψηφίδα τεχνολογίας FPGA επιταχυντών υλικού υψηλής απόδοσης για συμπίεση υπερφασματικών εικόνων εν πτήσει σε αεροδιαστημικά συστήματα

Antonis Tsigkanos

PhD thesis, 2021

A 3.3 Gbps CCSDS 123.0-B-1 Multispectral & Hyperspectral Image Compression Hardware Accelerator on a Space-Grade SRAM FPGA.

Antonis Tsigkanos, Nektarios Kranitis, George Theodorou, Antonis M. Paschalis

IEEE Trans. Emerg. Top. Comput., 2021

2020

High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1.

Antonis Tsigkanos, Nektarios Kranitis, Dimitris Theodoropoulos, Antonis M. Paschalis

IEEE Trans. Very Large Scale Integr. Syst., 2020

Efficient Architectures for Multigigabit CCSDS LDPC Encoders.

Dimitris Theodoropoulos, Nektarios Kranitis, Antonis Tsigkanos, Antonis M. Paschalis

IEEE Trans. Very Large Scale Integr. Syst., 2020

Efficient LDPC Encoder Designs for Magnetic Recording Media.

Dimitris Theodoropoulos, Nektarios Kranitis, Antonis Tsigkanos, Antonis M. Paschalis

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

Analyzing the Resilience to SEUs of an Image Data Compression Core in a COTS SRAM FPGA.

Ioannis Tsounis, Antonis Tsigkanos, Vasileios Vlagkoulis, Mihalis Psarakis, Nektarios Kranitis, Antonis M. Paschalis

Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2019

2015

A single chip dependable and adaptable payload Data Processing Unit.

Nektarios Kranitis, Antonis Tsigkanos, George Theodorou, Ioannis Sideris, Antonis M. Paschalis

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015