Nektarios Kranitis

Orcid: 0000-0002-0521-4433

According to our database1, Nektarios Kranitis authored at least 42 papers between 1999 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Online presence:

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Bibliography

2022
Efficient Hardware Architectures and Implementations of Packet-Level Erasure Coding Schemes for High Data Rate Reliable Satellite Communications.
IEEE Trans. Aerosp. Electron. Syst., 2022

An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology.
IEEE Trans. Aerosp. Electron. Syst., 2022

High-Performance Hardware Accelerators for Next Generation On-Board Data Processing.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2021
A 3.3 Gbps CCSDS 123.0-B-1 Multispectral & Hyperspectral Image Compression Hardware Accelerator on a Space-Grade SRAM FPGA.
IEEE Trans. Emerg. Top. Comput., 2021

2020
High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Efficient Architectures for Multigigabit CCSDS LDPC Encoders.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Efficient LDPC Encoder Designs for Magnetic Recording Media.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019
Analyzing the Resilience to SEUs of an Image Data Compression Core in a COTS SRAM FPGA.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2019

2016
An efficient LDPC encoder architecture for space applications.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015
A single chip dependable and adaptable payload Data Processing Unit.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

2014
Software-Based Self-Test for Small Caches in Microprocessors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Power-aware optimization of software-based self-test for L1 caches in microprocessors.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Dependable reconfigurable space systems: Challenges, new trends and case studies.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013
Software-Based Self Test Methodology for On-Line Testing of L1 Caches in Multithreaded Multicore Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2012
Low Energy Online Self-Test of Embedded Processors in Dependable WSN Nodes.
IEEE Trans. Dependable Secur. Comput., 2012

A Software-Based Self-Test methodology for on-line testing of data TLBs.
Proceedings of the 17th IEEE European Test Symposium, 2012

2011
A Software-Based Self-Test methodology for on-line testing of processor caches.
Proceedings of the 2011 IEEE International Test Conference, 2011

2010
A software-based self-test methodology for in-system testing of processor cache tag arrays.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

SBST for on-line detection of hard faults in multiprocessor applications under energy constraints.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Energy optimal on-line Self-Test of microprocessors in WSN nodes.
Proceedings of the 28th International Conference on Computer Design, 2010

2008
Hybrid-SBST Methodology for Efficient Testing of Processor Cores.
IEEE Des. Test Comput., 2008

Low Energy On-Line SBST of Embedded Processors.
Proceedings of the 2008 IEEE International Test Conference, 2008

Directed Random SBST Generation for On-Line Testing of Pipelined Processors.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

2007
Selecting Power-Optimal SBST Routines for On-Line Processor Testing.
Proceedings of the 12th European Test Symposium, 2007

2006
A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Optimal periodic testing of intermittent faults in embedded pipelined processor applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Αποδοτικές τεχνικές ενσωματωμένης αυτοδοκιμής για επεξεργαστές τεχνολογίας CMOS VLSI βασισμένες στην αρχιτεκτονική του συνόλου εντολών
PhD thesis, 2005

A concurrent built-in self-test architecture based on a self-testing RAM.
IEEE Trans. Reliab., 2005

Software-Based Self-Testing of Embedded Processors.
IEEE Trans. Computers, 2005

2003
Instruction-Based Self-Testing of Processor Cores.
J. Electron. Test., 2003

Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Low-Cost Software-Based Self-Testing of RISC Processor Cores.
Proceedings of the 2003 Design, 2003

2002
Effective Software Self-Test Methodology for Processor Cores.
Proceedings of the 2002 Design, 2002

2001
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths.
J. Electron. Test., 2001

Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Deterministic software-based self-testing of embedded processor cores.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Power-/Energy Efficient BIST Schemes for Processor Data Paths.
IEEE Des. Test Comput., 2000

Low Power/Energy BIST Scheme for Datapaths.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Deterministic Built-In Self -Test for Shifters, Adders and ALUs in Datapaths.
Proceedings of the 1st Latin American Test Workshop, 2000

Effective Low Power BIST for Datapaths.
Proceedings of the 2000 Design, 2000

1999
An Effective BIST Architecture for Fast Multiplier Cores.
Proceedings of the 1999 Design, 1999


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