Ari Paasio

According to our database, Ari Paasio authored at least 93 papers between 1994 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

High-Dynamic-Range Image Reconstruction from Pixel-Level Self-Reset ADC Samples.

Mika Grönroos, Ari Paasio, Mika Laiho

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Embedded processing methods for online visual analysis of laser welding.

Olli Lahdenoja, Tero Säntti, Jonne K. Poikonen, Mika Laiho, Ari Paasio, Joonas Pekkarinen, Antti Salminen

J. Real Time Image Process., 2019

2018

Implementation of a Fast and Low-Power Thermopile Readout Circuit Arrangement for Array Processors.

Mika Grönroos, Tapani Nevalainen, Ari Paasio

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Low-Power Regulator for Micro Energy Harvesting Applications.

Tapani Nevalainen, Esteban Ferro, Víctor M. Brea, Paula López, Ari Paasio

Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

2017

Local memory and logic arrangement for ultra-low power array processors.

Ari Paasio

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Fast thermopile readout circuit arrangement for array processors.

Mari Grönroos, Tapani Nevalainen, Jonne Poikonen, Ari Paasio

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A novel and systematic implementation of thermometer-coded current-mode DAC.

Mika Grönroos, Ari Paasio

Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016

Ultra low-power array processor propagation circuit arrangement.

Ari Paasio

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Seismocardiography: Toward heart rate variability (HRV) estimation.

Mojtaba Jafari Tadi, Eero Lehtonen, Tero Koivisto, Mikko Pänkäälä, Ari Paasio, Mika Teräs

Proceedings of the 2015 IEEE International Symposium on Medical Measurements and Applications, 2015

Online seam tracking for laser welding with a vision chip and FPGA enabled camera system.

Tero Säntti, Jonne K. Poikonen, Olli Lahdenoja, Mika Laiho, Ari Paasio

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Local asymmetric propagation stopper circuit for asynchronous binary wave computing.

Ari Paasio

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

Accelerometer-Based Method for Extracting Respiratory and Cardiac Gating Information for Dual Gating during Nuclear Medicine Imaging.

Mojtaba Jafari Tadi, Tero Koivisto, Mikko Pänkäälä, Ari Paasio

Int. J. Biomed. Imaging, 2014

Comparison of 130 nm technology 6T and 8T SRAM cell designs for Near-Threshold operation.

Mika Kutila, Ari Paasio, Teijo Lehtonen

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

CheckerBoard binary CNN core.

Ari Paasio

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Simulations on 130 nm technology 6T SRAM cell for Near-Threshold operation.

Mika Kutila, Ari Paasio, Teijo Lehtonen

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Seam tracking with adaptive image capture for fine-tuning of a high power laser welding process.

Olli Lahdenoja, Tero Säntti, Mika Laiho, Ari Paasio, Jonne K. Poikonen

Proceedings of the Seventh International Conference on Machine Vision, 2014

2013

Characterizing Spatters in Laser Welding of Thick Steel Using Motion Flow Analysis.

Olli Lahdenoja, Tero Säntti, Jonne Poikonen, Mika Laiho, Ari Paasio

Proceedings of the Image Analysis, 18th Scandinavian Conference, 2013

2011

Design Techniques and Considerations for a 1.2V 10bit CMOS Pipeline ADC.

Jia Sun, Hao Meng, Ari Paasio

Proceedings of the 13th UKSim-AMSS International Conference on Computer Modelling and Simulation, Cambridge University, Emmanuel College, Cambridge, UK, 30 March, 2011

Prototype rotation based assisted image analysis for 3D vision system.

Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A capacitor mismatch insensitive technique for RSD cyclic ADC.

Hao Meng, Ari Paasio, Jia Sun

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

Rate-distortion performance analysis of an analog motion estimation array.

Lauri Koskinen, Jonne Poikonen, Mika Laiho, Ari Paasio

Proceedings of the IEEE International Conference on Acoustics, 2010

2009

An 8times 8 Cell Analog Order-Statistic-Filter Array With Asynchronous Grayscale Morphology in 0.13-muhboxm CMOS.

Jonne Poikonen, Ari Paasio

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Effect of Mismatch on the Reliability of ON/OFF-Programmable CNNs.

Mika Laiho, Víctor M. Brea, Ari Paasio

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation.

Jonne Poikonen, Mika Laiho, Ari Paasio, Lauri Koskinen, Kari Halonen

EURASIP J. Adv. Signal Process., 2009

Temperature behavior of combination selection based mismatch calibration with 65 nm CMOS technology.

Joona Marku, Jonne Poikonen, Ari Paasio

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

On the Spatial Distribution of Local Non-parametric Facial Shape Descriptors.

Olli Lahdenoja, Mika Laiho, Ari Paasio

Proceedings of the Image Analysis, 16th Scandinavian Conference, 2009

MIPA4k: A 64×64 Cell Mixed-mode Image Processor Array.

Jonne Poikonen, Mika Laiho, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Temperature Compensation in Combination Selection based Mismatch Calibration.

Joona Marku, Jonne Poikonen, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Live Demonstration: MIPA4k: A 64×64 Cell Mixed-mode Image Processor Array.

Mika Laiho, Jonne Poikonen, Peter Virta, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Locally adaptive image sensing with the 64x64 cell MIPA4k mixed-mode image processor array.

Jonne Poikonen, Mika Laiho, Ari Paasio

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Space-dependent binary image processing within a 64x64 mixed-mode array processor.

Mika Laiho, Jonne Poikonen, Ari Paasio

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008

A Differential Architecture for an Online Analog Viterbi Decoder.

Janne Maunu, Mika Laiho, Ari Paasio

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Template Design for Cellular Nonlinear Networks With 1-Bit Weights.

Mika Laiho, Ari Paasio, Jacek Flak, Kari Halonen

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Centroiding and classification of objects using a processor array with a scalable region of interest.

Mika Laiho, Jonne Poikonen, Ari Paasio, Kari Halonen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Mixed-signal baseband processing chain for a MB-OFDM receiver.

Janne Maunu, Mika Laiho, Tero Koivisto, Kati Virtanen, Mikko Pänkäälä, Ari Paasio

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

CNN-type algorithms for H.264 variable block-size partitioning.

Lauri Koskinen, Ari Paasio, Kari Halonen

Signal Process. Image Commun., 2007

A Massively Parallel Face Recognition System.

Olli Lahdenoja, Mika Laiho, Janne Maunu, Ari Paasio

EURASIP J. Embed. Syst., 2007

A 12-bit Current-Steering DAC with Calibration by Combination Selection.

Kati Virtanen, Janne Maunu, Jonne Poikonen, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Architecture for Analog Variable Block-Size Motion Estimation.

Lauri Koskinen, Joona Marku, Ari Paasio, Kari Halonen

Proceedings of the International Conference on Image Processing, 2007

Relating Cellular Non-linear Networks to Threshold Logic and Single Instruction Multiple Data computing models.

Víctor M. Brea, Mika Laiho, Natalia A. Fernandez-Garcia, Ari Paasio, Diego Cabello

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

An Analog 2-D DCT Processor.

Mikko Pänkäälä, Kati Virtanen, Ari Paasio

IEEE Trans. Circuits Syst. Video Technol., 2006

Dense CMOS implementation of a binary-programmable cellular neural network.

Jacek Flak, Mika Laiho, Ari Paasio, Kari Halonen

Int. J. Circuit Theory Appl., 2006

A binary-based on-chip CNN solution for pixel-level snakes.

Víctor M. Brea, Mika Laiho, David López Vilariño, Ari Paasio, Diego Cabello

Int. J. Circuit Theory Appl., 2006

An On-Chip Measurement Circuit for Calibration by Combination Selection.

Janne Maunu, Joona Marku, Mika Laiho, Ari Paasio

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Implementation of an asynchronous current-mode ADC with adaptive quantization.

Kati Virtanen, Mikko Pänkäälä, Mika Laiho, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On the topographic equivalence between voltage mode and current mode ranked order filters for array processors.

Jonne Poikonen, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Current source calibration by combination selection of minimum sized devices.

Janne Maunu, Mikko Pänkäälä, Joona Marku, Jonne Poikonen, Mika Laiho, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Effect of mismatch on the reliability of binary-programmable CNNs.

Mika Laiho, Ari Paasio, Víctor M. Brea

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A massively parallel algorithm for local binary pattern based face recognition.

Olli Lahdenoja, Janne Maunu, Mika Laiho, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Sine wave as a correlating signal for UWB radio.

Tero Koivisto, Teemu Peltonen, Meigen Shen, Esa Tjukanoff, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Shape-Preserving Non-parametric Symmetry Transform.

Olli Lahdenoja, Esa Alhoniemi, Mika Laiho, Ari Paasio

Proceedings of the 18th International Conference on Pattern Recognition (ICPR 2006), 2006

2005

Motion estimation computational complexity reduction with CNN shape segmentation.

Lauri Koskinen, Ari Paasio, Kari Halonen

IEEE Trans. Circuits Syst. Video Technol., 2005

A current-mode ADC with adaptive quantization.

Kati Virtanen, Mikko Pänkäälä, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Compensation of errors generated by an analog 2D DCT.

Kati Virtanen, N. Pankaala, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Gray-coded digital-to-analog converter for a mixed-mode processor array.

Laura Vesalainen, Jonne Poikonen, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Rank identification for an analog ranked order filter.

Jonne Poikonen, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Template design for binary-programmable cellular nonlinear networks.

Mika Laiho, Ari Paasio, Jacek Flak, Kari Halonen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Dynamically coupled multi-layer mixed-mode CNN.

Mika Laiho, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Effect of mismatch on a ranked-order extractor array [image processing applications].

Olli Lahdenoja, Jonne Poikonen, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Parallel processor algorithm for variable block-size computation at low bitrates [video coding applications].

Lauri Koskinen, Kari Halonen, Ari Paasio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing.

Víctor M. Brea, Mika Laiho, David López Vilariño, Ari Paasio, Diego Cabello

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A one-quadrant discrete-time cellular neural network CMOS chip for pixel-level snakes.

Víctor M. Brea, Mika Laiho, David López Vilariño, Ari Paasio, Diego Cabello

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Reducing the feature vector length in local binary pattern based face recognition.

Olli Lahdenoja, Mika Laiho, Ari Paasio

Proceedings of the 2005 International Conference on Image Processing, 2005

A simple variable λ resistive network implementation.

Asko Kananen, Ari Paasio, Kari Halonen

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Robustness improvement in binary cellular non-linear network architectures.

Víctor M. Brea, Mika Laiho, Ari Paasio

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004

A ranked order filter implementation for parallel analog processing.

Jonne Poikonen, Ari Paasio

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A mixed-mode polynomial cellular array processor hardware realization.

Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Design of the processing core of a mixed-signal CMOS DTCNN chip for pixel-level snakes.

Víctor M. Brea, David López Vilariño, Ari Paasio, Diego Cabello

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A gray-code current-mode ADC for mixed-mode cellular computer.

Laura Vesalainen, Jonne Poikonen, Mikko Pänkäälä, Ari Paasio

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Realization of an analog current-mode 2D DCT.

Mikko Pänkäälä, Jonne Poikonen, Laura Vesalainen, Ari Paasio

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

High density VLSI implementation of a bipolar CNN with reduced programmability.

Ari Paasio, Jacek Flak, Mika Laiho, Kari Halonen

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Improved cell core for a mixed-mode polynomial CNN.

Mika Laiho, Ari Paasio, Kari Halonen

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

3-neighborhood motion estimation in CNN silicon architectures.

Lauri Koskinen, Ari Paasio, Kari Halonen

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

N × 16 cellular test chips for low-pass filtering large images.

Asko Kananen, Mika Laiho, Kari Halonen, Ari Paasio

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Realization of Couplings in a Polynomial Type Mixed-Mode Cellular Neural Network.

Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen

Int. J. Neural Syst., 2003

CNN shape segmentation advantages in MPEG-4 simple profile encoding.

Lauri Koskinen, Ari Paasio, Kari Halonen

Proceedings of the Seventh International Symposium on Signal Processing and Its Applications, 2003

An area-efficient full-wave current rectifier for analog array processing.

Jonne Poikonen, Ari Paasio

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 32×32 cellular test chip targeting new functionalities.

Ari Paasio, Mika Laiho, Asko Kananen, Kari Halonen, Jonne Poikonen

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

A mixed-mode polynomial-type CNN for analysing brain electrical activity in epilepsy.

Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen

Int. J. Circuit Theory Appl., 2002

CNN applications from the hardware point of view: video sequence segmentation.

Asko Kananen, Ari Paasio, Mika Laiho, Kari Halonen

Int. J. Circuit Theory Appl., 2002

Cell and network level design of a mixed-mode CNN.

Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Effect of CNN shape segmentation on MPEG-4 shape bit-rate.

Lauri Koskinen, Ari Paasio, Mika Laiho, Kari Halonen

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Implementation oriented theory design issues on the DTCNN template generation.

Víctor M. Brea, David López Vilariño, Ari Paasio, Diego Cabello

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

Discrete time analog polynomial type CNN with digital state.

Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

A multiplier-free fixed-task digital CNN array for video segmentation system.

Ari Paasio, Jani Paakkulainen, Jouni Isoaho

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Building blocks for large annealed compact neural networks.

Mika Laiho, Ari Paasio, Kari Halonen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

A QCIF Resolution Binary I/O CNN-UM Chip.

Ari Paasio, Asko Kananen, Kari Halonen, Veikko Porra

J. VLSI Signal Process., 1999

CNN template robustness with different output nonlinearities.

Ari Paasio, Adam Dawidziuk

Int. J. Circuit Theory Appl., 1999

Very fast and compact fixed template CNN realizations for B/W processing.

Ari Paasio, Asko Kananen, Kari Halonen

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

A 48 by 48 CNN chip operating with B/W images.

Ari Paasio, Asko Kananen, Kari Halonen, Veikko Porra

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1996

Implementation of cellular neural network operating with bipolar images.

Ari Paasio, Adam Dawidziuk, Veikko Porra

Proceedings of International Conference on Neural Networks (ICNN'96), 1996

VLSI implementation of cellular neural network universal machine.

Ari Paasio, Adam Dawidziuk, Veikko Porra

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1994

CMOS Implementation of Associative Memory Using Cellular Neural Network Having Adjustable Template Coefficients.

Ari Paasio, Kari Halonen, Veikko Porra

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994