Mika Laiho

According to our database1, Mika Laiho authored at least 79 papers between 2000 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
High-Dynamic-Range Image Reconstruction from Pixel-Level Self-Reset ADC Samples.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Embedded processing methods for online visual analysis of laser welding.
J. Real Time Image Process., 2019

Memristive Stateful Logic.
Proceedings of the Handbook of Memristor Networks., 2019

2017
A mixed-mode array computing architecture for online dictionary learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Associative search using pseudo-analog memristors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Associative memory with occurrence statistics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Hidden Markov model inference in an Associative memory architecture.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

Recursive functions in high-dimensional computing with random vectors.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

A Performance Case-Study on Memristive Computing-in-Memory Versus Von Neumann Architecture.
Proceedings of the 2016 Data Compression Conference, 2016

2015
FPAA/Memristor Hybrid Computing Infrastructure.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Recursive Algorithms in Memristive Logic Arrays.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Online seam tracking for laser welding with a vision chip and FPGA enabled camera system.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Implementation of nondeterministic finite automata in an autoassociative CAM circuit.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 512×512-cell associative CAM/Willshaw memory with vector arithmetic.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

High-dimensional computing with sparse vectors.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
Large-Scale Memristive Associative Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A cellular computing architecture for parallel memristive stateful logic.
Microelectron. J., 2014

Memristive Circuits for LDPC Decoding.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Analog signal processing on a FPAA/memristor hybrid circuit.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Seam tracking with adaptive image capture for fine-tuning of a high power laser welding process.
Proceedings of the Seventh International Conference on Machine Vision, 2014

2013
Characterizing Spatters in Laser Welding of Thick Steel Using Motion Flow Analysis.
Proceedings of the Image Analysis, 18th Scandinavian Conference, 2013

2012
On Synthesis of Boolean Expressions for Memristive Devices Using Sequential Implication Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Fault-tolerant programmable logic array for nanoelectronics.
Int. J. Circuit Theory Appl., 2012

Implication logic synthesis methods for memristors.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Memristive analog arithmetic within cellular arrays.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Time-dependency of the threshold voltage in memristive devices.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
A CNN approach to computing arbitrary Boolean functions.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Cellular nanoscale network cell with memristors for local implication logic and synapses.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Rate-distortion performance analysis of an analog motion estimation array.
Proceedings of the IEEE International Conference on Acoustics, 2010

2009
A Micropower Front End for Three-Axis Capacitive Microaccelerometers.
IEEE Trans. Instrum. Meas., 2009

Effect of Mismatch on the Reliability of ON/OFF-Programmable CNNs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation.
EURASIP J. Adv. Signal Process., 2009

On the Spatial Distribution of Local Non-parametric Facial Shape Descriptors.
Proceedings of the Image Analysis, 16th Scandinavian Conference, 2009

Stateful implication logic with memristors.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

MIPA4k: A 64×64 Cell Mixed-mode Image Processor Array.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Live Demonstration: MIPA4k: A 64×64 Cell Mixed-mode Image Processor Array.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Compact floating-gate learning array with STDP.
Proceedings of the International Joint Conference on Neural Networks, 2009

Locally adaptive image sensing with the 64x64 cell MIPA4k mixed-mode image processor array.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Space-dependent binary image processing within a 64x64 mixed-mode array processor.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Regional image correspondence matching method for SIMD processing.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A ring-oscillator-based active quenching and active recharge circuit for single photon avalanche diodes.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
A Differential Architecture for an Online Analog Viterbi Decoder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Template Design for Cellular Nonlinear Networks With 1-Bit Weights.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Centroiding and classification of objects using a processor array with a scalable region of interest.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Mixed-signal baseband processing chain for a MB-OFDM receiver.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
A Micropower Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer.
IEEE J. Solid State Circuits, 2007

A Massively Parallel Face Recognition System.
EURASIP J. Embed. Syst., 2007

A 62μA Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Micropower Voltage, Current, and Temperature Reference for a Low-Power Capacitive Sensor Interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A nanopower double-mode 1-V frequency reference for an ultra-low-power capacitive sensor interface.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Relating Cellular Non-linear Networks to Threshold Logic and Single Instruction Multiple Data computing models.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
Dense CMOS implementation of a binary-programmable cellular neural network.
Int. J. Circuit Theory Appl., 2006

A binary-based on-chip CNN solution for pixel-level snakes.
Int. J. Circuit Theory Appl., 2006

An On-Chip Measurement Circuit for Calibration by Combination Selection.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Implementation of an asynchronous current-mode ADC with adaptive quantization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 3µW, 2 MHz CMOS frequency reference for capacitive sensor applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Current source calibration by combination selection of minimum sized devices.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Effect of mismatch on the reliability of binary-programmable CNNs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A massively parallel algorithm for local binary pattern based face recognition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Shape-Preserving Non-parametric Symmetry Transform.
Proceedings of the 18th International Conference on Pattern Recognition (ICPR 2006), 2006

2005
Template design for binary-programmable cellular nonlinear networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Dynamically coupled multi-layer mixed-mode CNN.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A one-quadrant discrete-time cellular neural network CMOS chip for pixel-level snakes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Reducing the feature vector length in local binary pattern based face recognition.
Proceedings of the 2005 International Conference on Image Processing, 2005

A micropower 2 MHz CMOS frequency reference for capacitive sensor applications.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Robustness improvement in binary cellular non-linear network architectures.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
A mixed-mode polynomial cellular array processor hardware realization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

High density VLSI implementation of a bipolar CNN with reduced programmability.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Improved cell core for a mixed-mode polynomial CNN.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

N × 16 cellular test chips for low-pass filtering large images.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Realization of Couplings in a Polynomial Type Mixed-Mode Cellular Neural Network.
Int. J. Neural Syst., 2003

A 32×32 cellular test chip targeting new functionalities.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
A mixed-mode polynomial-type CNN for analysing brain electrical activity in epilepsy.
Int. J. Circuit Theory Appl., 2002

CNN applications from the hardware point of view: video sequence segmentation.
Int. J. Circuit Theory Appl., 2002

Cell and network level design of a mixed-mode CNN.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Effect of CNN shape segmentation on MPEG-4 shape bit-rate.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Discrete time analog polynomial type CNN with digital state.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Building blocks for large annealed compact neural networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


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