Jani Paakkulainen

According to our database1, Jani Paakkulainen authored at least 7 papers between 2000 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2009
Outline of RISC-based core for multiprocessor on chip architecture supporting moving threads.
Proceedings of the 2009 International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, 2009

MVTsim: software simulator for multicore on chip parallel computer architectures.
Proceedings of the 2009 International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, 2009

2005
A system-level framework for designing and evaluating protocol processor architectures.
Int. J. Embed. Syst., 2005

Tuning a Protocol Processor Architecture Towards DSP Operations.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Highly Automated FPGA Synthesis of Application-Specific Protocol Processors.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Capturing Processor Architectures from Protocol Processing Applications: a Case Study.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2000
A multiplier-free fixed-task digital CNN array for video segmentation system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


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