Arindam Banerjee

According to our database, Arindam Banerjee authored at least 13 papers between 2011 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A Novel ALU Circuit based on Reversible Logic.

Arindam Banerjee, Debesh Kumar Das

J. Circuits Syst. Comput., 2020

2019

Arithmetic Circuits Using Reversible Logic: A Survey Report.

Arindam Banerjee, Debesh Kumar Das

Proceedings of the Advanced Computing and Systems for Security, 2019

2016

A New Squarer design with reduced area and delay.

Arindam Banerjee, Debesh Kumar Das

IET Comput. Digit. Tech., 2016

Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs.

Arindam Banerjee, Debesh Kumar Das

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A new ALU architecture design using reversible logic.

Arindam Banerjee, Debesh Kumar Das

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

2015

The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics.

Arindam Banerjee, Debesh Kumar Das

J. Low Power Electron., 2015

Squarer design with reduced area and delay.

Arindam Banerjee, Debesh Kumar Das

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014

Improved matrix multiplier design for high-speed digital signal processing applications.

Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat

IET Circuits Devices Syst., 2014

Squaring in reversible logic using iterative structure.

Arindam Banerjee, Debesh Kumar Das

Proceedings of the 2014 East-West Design & Test Symposium, 2014

2013

The Design of Reversible Multiplier Using Ancient Indian Mathematics.

Arindam Banerjee, Debesh Kumar Das

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

2012

Design of High Speed Vedic Multiplier for Decimal Number System.

Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

2011

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics.

Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya

Microelectron. J., 2011

Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications.

Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat

Proceedings of the International Symposium on Electronic System Design, 2011