Debesh Kumar Das

According to our database, Debesh Kumar Das authored at least 99 papers between 1993 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

IRUVD: a new still-image based dataset for automatic vehicle detection.

Asfak Ali, Ram Sarkar, Debesh Kumar Das

Multim. Tools Appl., January, 2024

Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs.

Tanusree Kaibartta, Hitarth Arora, Debesh Kumar Das

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2022

A new online testing technique for reversible circuits.

Joyati Mondal, Debesh Kumar Das

IET Quantum Commun., March, 2022

DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits.

Joyati Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh Kumar Das, Bhargab B. Bhattacharya

J. Circuits Syst. Comput., 2022

Improved Upper Bound on Independent Domination Number for Hypercubes.

Debabani Chowdhury, Debesh K. Das, Bhargab B. Bhattacharya

CoRR, 2022

Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking.

Habibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect.

Subrata Das, Debesh Kumar Das, Soumya Pandit

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021

An Efficient Design for Testability Approach of Reversible Logic Circuits.

Joyati Mondal, Arighna Deb, Debesh K. Das

J. Circuits Syst. Comput., 2021

Fast algorithms for test optimization of core based 3D SoC.

Sabyasachee Banerjee, Subhashis Majumder, Debesh K. Das, Bhargab B. Bhattacharya

Integr., 2021

A Genetic Algorithm-Based Metaheuristic Approach for Test Cost Optimization of 3D SIC.

Tanusree Kaibartta, G. P. Biswas, Arup Kumar Pal, Debesh Kumar Das

IEEE Access, 2021

Minimization of Switching Activity of Graphene Based Circuits.

Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

2020

A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects.

Subrata Das, Debesh Kumar Das, Soumya Pandit

ACM J. Emerg. Technol. Comput. Syst., 2020

A Novel ALU Circuit based on Reversible Logic.

Arindam Banerjee, Debesh Kumar Das

J. Circuits Syst. Comput., 2020

Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs.

Tanusree Kaibartta, G. P. Biswas, Debesh Kumar Das

J. Electron. Test., 2020

An Improved Online Testing Technique For Reversible Circuits.

Joyati Mondal, Debesh Kumar Das

Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

Heuristic Approach for Identification of Random TSV Defects in 3D IC During Pre-bond Testing.

Tanusree Kaibartta, G. P. Biswas, Debesh K. Das

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits.

Joyati Mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh Kumar Das

J. Circuits Syst. Comput., 2019

Approach of genetic algorithm for power-aware testing of 3D IC.

Tanusree Kaibartta, Chandan Giri, Hafizur Rahaman, Debesh Kumar Das

IET Comput. Digit. Tech., 2019

Delay Efficient All Optical Carry Lookahead Adder.

Sayantani Roy, Arighna Deb, Debesh K. Das

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Detailed Fault Model for Physical Quantum Circuits.

Arighna Deb, Debesh K. Das

Proceedings of the 28th IEEE Asian Test Symposium, 2019

Arithmetic Circuits Using Reversible Logic: A Survey Report.

Arindam Banerjee, Debesh Kumar Das

Proceedings of the Advanced Computing and Systems for Security, 2019

2018

Optimization of Test Wrapper Length for TSV Based 3D SOCs Using a Heuristic Approach.

Tanusree Kaibartta, Debesh Kumar Das

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

Floorplanning in Graphene Nanoribbon (GNR) Based Circuits.

Subrata Das, Debesh Kumar Das

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata.

Arighna Deb, Debesh K. Das

Microprocess. Microsystems, 2017

A technique to construct global routing trees for graphene nanoribbon (GNR).

Subrata Das, Debesh Kumar Das

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A placement optimization technique for 3D IC.

Sabyasachee Banerjee, Subhashis Majumder, Abhishek Varma, Debesh K. Das

Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

Design for Testability Technique of Reversible Logic Circuits Based on Exclusive Testing.

Joyati Mondal, Debesh Kumar Das

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability.

Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya

ACM J. Emerg. Technol. Comput. Syst., 2016

A New Squarer design with reduced area and delay.

Arindam Banerjee, Debesh Kumar Das

IET Comput. Digit. Tech., 2016

Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs.

Arindam Banerjee, Debesh Kumar Das

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff.

Debasis Pal, Abir Pramanik, Parthasarathi Dasgupta, Debesh Kumar Das

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults.

Debabani Chowdhury, Debesh K. Das, Bhargab B. Bhattacharya, Tsutomu Sasao

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

A new ALU architecture design using reversible logic.

Arindam Banerjee, Debesh Kumar Das

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees.

Subrata Das, Soma Das, Adrija Majumder, Parthasarathi Dasgupta, Debesh Kumar Das

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

A rule-based approach for minimizing power dissipation of digital circuits.

Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh, Debesh Kumar Das

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics.

Arindam Banerjee, Debesh Kumar Das

J. Low Power Electron., 2015

One More Class of Sequential Circuits having Combinational Test Generation Complexity.

Debesh Kumar Das, Hideo Fujiwara

J. Electron. Test., 2015

Partitioning-based test time reduction for core-based 3DICs.

Sabyasachee Banerjee, Subhashis Majumder, Debesh K. Das

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Squarer design with reduced area and delay.

Arindam Banerjee, Debesh Kumar Das

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization.

Arighna Deb, Robert Wille, Rolf Drechsler, Debesh K. Das

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Testing of 3D IC with minimum power using genetic algorithm.

Tanusree Kaibartta, Debesh K. Das

Proceedings of the 10th International Design & Test Symposium, 2015

Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits.

Joyati Mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Design-for-testability in reversible logic circuits based on bit-swapping.

Joyati Mondal, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic.

Arighna Deb, Debesh Kumar Das, Susmita Sur-Kolay

J. Low Power Electron., 2014

A regular network of symmetric functions in quantum-dot cellular automata.

Arighna Deb, Debesh Kumar Das

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties.

Rupali Mitra, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Inadmissible Class of Boolean Functions under Stuck-at Faults.

Debesh K. Das, Debabani Chowdhury, Bhargab B. Bhattacharya, Tsutomu Sasao

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Synthesis of Symmetric Boolean Functions Using a Three-Stage Network.

Arighna Deb, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning.

Manjari Pradhan, Debesh K. Das, Chandan Giri, Hafizur Rahaman

Proceedings of the 2014 East-West Design & Test Symposium, 2014

Squaring in reversible logic using iterative structure.

Arindam Banerjee, Debesh Kumar Das

Proceedings of the 2014 East-West Design & Test Symposium, 2014

Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method.

Bappaditya Mondal, Dipak Kumar Kole, Debesh Kumar Das, Hafizur Rahaman

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Derivation of test set for detecting multiple missing-gate faults in reversible circuits.

Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya

Comput. Electr. Eng., 2013

On Designing Testable Reversible Circuits Using Gate Duplication.

Joyati Mondal, Debesh Kumar Das, Dipak Kumar Kole, Hafizur Rahaman, Bhargab B. Bhattacharya

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure.

Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler

Proceedings of the Reversible Computation - 5th International Conference, 2013

Modular Design for Symmetric Functions Using Quantum Quaternary Logic.

Arighna Deb, Debesh K. Das, Susmita Sur-Kolay

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

The Design of Reversible Multiplier Using Ancient Indian Mathematics.

Arindam Banerjee, Debesh Kumar Das

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Reversible synthesis of symmetric boolean functions based on unate decomposition.

Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

A design for testability technique for quantum reversible circuits.

Joyati Mondal, Debesh K. Das, Dipak Kumar Kole, Hafizur Rahaman

Proceedings of the East-West Design & Test Symposium, 2013

Optimal stacking of SOCs in a 3D-SIC for post-bond testing.

Manjari Pradhan, Chandan Giri, Hafizur Rahaman, Debesh K. Das

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

Reversible Logic Circuit Synthesis Using Genetic Algorithm and Particle Swarm Optimization.

Papia Manna, Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the International Symposium on Electronic System Design, 2012

2011

Fault diagnosis in reversible circuits under missing-gate fault model.

Hafizur Rahaman, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya

Comput. Electr. Eng., 2011

Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs.

Surajit Kumar Roy, Chandan Giri, Arnab Chakraborty, Subhro Mukherjee, Debesh K. Das, Hafizur Rahaman

Proceedings of the International Symposium on Electronic System Design, 2011

Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits.

Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the International Symposium on Electronic System Design, 2011

2010

Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits.

Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Testable design of AND-EXOR logic networks with universal test sets.

Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya

Comput. Electr. Eng., 2009

2008

An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell.

Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya

IEEE Trans. Instrum. Meas., 2008

On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set.

Hafizur Rahaman, Dipak Kumar Kole, Debesh Kumar Das, Bhargab B. Bhattacharya

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

Optimum Test Set for Bridging Fault Detection in Reversible Circuits.

Hafizur Rahaman, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the 16th Asian Test Symposium, 2007

2006

Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability.

Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya

J. Electron. Test., 2006

2005

A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area.

Biplab K. Sikdar, Samir Roy, Debesh K. Das

J. Electron. Test., 2005

Cellular Automata Based Test Structures with Logic Folding.

Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Synthesis of Testable Finite State Machine Through Decomposition.

Biplab K. Sikdar, Arijit Sarkar, Samir Roy, Debesh K. Das

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA.

Hafizur Rahaman, Debesh K. Das

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency.

Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara

J. Electron. Test., 2004

Design & Test Education in Asia.

Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian

IEEE Des. Test Comput., 2004

Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults.

Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity.

Debesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults.

Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A Simple Delay Testable Synthesis of Symmetric Functions.

Hafizur Rahaman, Debesh K. Das

Proceedings of the Applied Computing, Second Asian Applied Computing Conference, 2004

2003

Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability.

Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count.

Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya

J. Comput. Sci. Technol., 2002

Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area.

Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

A New Synthesis of Symmetric Functions.

Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001

Hierarchical Cellular Automata As An On-Chip Test Pattern Generator.

Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Testable Design of Sequential Circuits with Improved Fault Efficiency.

Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis.

Biplab K. Sikdar, Samir Roy, Debesh K. Das

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Cellular automata as a built in self test structure.

Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri

Proceedings of ASP-DAC 2001, 2001

2000

Synthesis of symmetric functions for path-delay fault testability.

Susanta Chakrabarti, Sandip Das, Debesh Kumar Das, Bhargab B. Bhattacharya

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Isomorph-Redundancy in Sequential Circuits.

Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya

IEEE Trans. Computers, 2000

Test Generation for Acyclic Sequential Circuits with Hold Registers.

Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999

Synthesis of Symmetric Functions for Path-Delay Fault Testability.

Susanta Chakraborty, Sandip Das, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency.

Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits.

Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults.

Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits.

Debesh K. Das, Susanta Chakraborty, Bhargab B. Bhattacharya

Proceedings of the ASP-DAC '98, 1998

1997

New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults.

Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

Does retiming affect redundancy in sequential circuits?

Debesh Kumar Das, Bhargab B. Bhattacharya

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995

Testable design of non-scan sequential circuits using extra logic.

Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1993

Logical redundancies in irredundant combinational circuits.

Susanta Chakraborty, Debesh Kumar Das, Bhargab B. Bhattacharya

J. Electron. Test., 1993