Anup Dandapat

According to our database1, Anup Dandapat authored at least 25 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 





Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Novel Low-Power Matchline Evaluation Technique for Content Addressable Memory (CAM).
J. Inf. Sci. Eng., 2020

Low-power content addressable memory design using two-layer P-N match-line control and sensing.
Integr., 2020

The analogy of matchline sensing techniques for content addressable memory (CAM).
IET Comput. Digit. Tech., 2020

Low discharge precharge free matchline structure for energy-efficient search using CAM.
Integr., 2019

A Low-Power Split-Controlled Single Ended Storage Content Addressable Memory.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory.
IEEE Trans. Consumer Electron., 2018

A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Self-Controlled High-Performance Precharge-Free Content-Addressable Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Energy-Efficient Adaptive Match-Line Controller for Large-Scale Associative Storage.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Novel Methodology for Design of Cyclic Combinational Circuits.
J. Low Power Electron., 2016

Design Methodology for Multiple Output Combinational Circuits Using Cyclic Combinational Technique.
J. Circuits Syst. Comput., 2016

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique.
J. Signal Process. Syst., 2014

Design of 64-Bit Squarer Based on Vedic Mathematics.
J. Circuits Syst. Comput., 2014

Improved matrix multiplier design for high-speed digital signal processing applications.
IET Circuits Devices Syst., 2014

A Novel Design of Seven Segment Decoder Using Cyclic Combinational Technique.
J. Low Power Electron., 2013

Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Design of High Speed Vedic Multiplier for Decimal Number System.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics.
Microelectron. J., 2011

Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications.
Proceedings of the International Symposium on Electronic System Design, 2011

Design of a Low Leakage, Low Power and High Performance Search and Read Memory Using CAM and SRAM.
J. Low Power Electron., 2008