Arshad Aziz

According to our database, Arshad Aziz authored at least 27 papers between 2007 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

An Efficient IIoT-Based Smart Sensor Node for Predictive Maintenance of Induction Motors.

Majida Kazmi, Maria Tabasum Shoaib, Arshad Aziz, Hashim Raza Khan, Saad Ahmed Qazi

Comput. Syst. Sci. Eng., 2023

Code-Switched Urdu ASR for Noisy Telephonic Environment using Data Centric Approach with Hybrid HMM and CNN-TDNN.

Muhammad Danyal Khan, Raheem Ali, Arshad Aziz

CoRR, 2023

2020

Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3.

Dur-e-Shahwar Kundi, Ayesha Khalid, Arshad Aziz, Chenghua Wang, Máire O'Neill, Weiqiang Liu

IEEE Trans. Circuits Syst., 2020

Resource-Efficient Image Buffer Architecture for Neighborhood Processors.

Majida Kazmi, Arshad Aziz, Hashim Raza Khan, Saad Ahmed Qazi, Lampros K. Stergioulas

IEEE Access, 2020

2019

An efficient and compact row buffer architecture on FPGA for real-time neighbourhood image processing.

Majida Kazmi, Arshad Aziz, Pervez Akhtar

J. Real Time Image Process., 2019

A Pareto-Optimal Multi-filter Architecture on FPGA for Image Processing Applications.

Majida Kazmi, Arshad Aziz, Dur-e-Shahwar Kundi

Circuits Syst. Signal Process., 2019

2018

A new rectangular window based image cropping method for generalization of brain neoplasm classification systems.

Razia Zia, Pervez Akhtar, Arshad Aziz

Int. J. Imaging Syst. Technol., 2018

Multi-resolution transforms-based hybrid feature extraction technique for differentiating glioma grades.

Razia Zia, Pervez Akhtar, Arshad Aziz, Dur-e-Shahwar Kundi

Int. J. Wavelets Multiresolution Inf. Process., 2018

2017

Non Sub-sampled Contourlet Transform Based Feature Extraction Technique for Differentiating Glioma Grades Using MRI Images.

Razia Zia, Pervez Akhtar, Arshad Aziz, Maroof Ali Shah, Dur-e-Shahwar Kundi

Proceedings of the AI 2017: Advances in Artificial Intelligence, 2017

2016

A high performance ST-Box based unified AES encryption/decryption architecture on FPGA.

Dur-e-Shahwar Kundi, Arshad Aziz, Nassar Ikram

Microprocess. Microsystems, 2016

A low-power SHA-3 designs using embedded digital signal processing slice on FPGA.

Dur-e-Shahwar Kundi, Arshad Aziz

Comput. Electr. Eng., 2016

2015

An efficient single unit T-box/T^-1-box implementation for 128-bit AES on FPGA.

Dur-e-Shahwar Kundi, Arshad Aziz, Majida Kazmi

Secur. Commun. Networks, 2015

2013

Simulation design of an efficient MTI processing module for embedded platform.

Munaza Yousuf, Riaz Mahmud, Arshad Aziz

Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

Software implementation of Standard Hash Algorithm (SHA-3) Keccak on Intel core-i5 and Cavium Networks Octeon Plus embedded platform.

Aisha Malik, Arshad Aziz, Dur-e-Shahwar Kundi, Moiz Akhter

Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

2012

Look-Up Table Based Implementations of SHA-3 Finalists: JH, Keccak and Skein.

Kashif Latif, Arshad Aziz, Athar Mahboob

KSII Trans. Internet Inf. Syst., 2012

Comparative Analysis of High Speed and Low Area Architectures of Blake SHA-3 Candidate on FPGA.

Muhammad Arsalan, Arshad Aziz

Proceedings of the 10th International Conference on Frontiers of Information Technology, 2012

Medical image denoising based on adaptive thresholding in contourlet domain.

Majida Kazmi, Arshad Aziz, Pervez Akhtar, Aliza Maftun, Wasay Bin Afaq

Proceedings of the 5th International Conference on BioMedical Engineering and Informatics, 2012

Novel Arithmetic Architecture for High Performance Implementation of SHA-3 Finalist Keccak on FPGA Platforms.

Kashif Latif, M. Muzaffar Rao, Athar Mahboob, Arshad Aziz

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

Optimal utilization of available reconfigurable hardware resources.

Kashif Latif, Arshad Aziz, Athar Mahboob

Comput. Electr. Eng., 2011

Efficient Hardware Implementation of Secure Hash Algorithm (SHA-3) Finalist - Skein.

Kashif Latif, Muhammad Tariq, Arshad Aziz, Athar Mahboob

Proceedings of the Frontiers in Computer Education [International Conference on Frontiers in Computer Education, 2011

High Throughput Hardware Implementation of Secure Hash Algorithm (SHA-3) Finalist: BLAKE.

Kashif Latif, Athar Mahboob, Arshad Aziz

Proceedings of the 2011 Frontiers of Information Technology, 2011

2010

Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA.

Dur-e-Shahwar Kundi, Arshad Aziz, Nassar Ikram

Inf. Process. Lett., 2010

2009

Efficient resource utilization of FPGAs.

Kashif Latif, Arshad Aziz, Athar Mahboob

Proceedings of the FIT '09, 2009

2007

Memory Efficient Implementation of AES S-Boxes on FPGA.

Arshad Aziz, Nassar Ikram

J. Circuits Syst. Comput., 2007

An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture.

Arshad Aziz, Nassar Ikram

Int. J. Netw. Secur., 2007

A Look-Up-Table Implementation of AES.

Arshad Aziz, Nassar Ikram

Proceedings of the International Conference on High Performance Computing, 2007

An Efficient Software Implementation of AES-CCM for IEEE 802.11i Wireless St.

Abdul Samiah, Arshad Aziz, Nassar Ikram

Proceedings of the 31st Annual International Computer Software and Applications Conference, 2007