Dur-e-Shahwar Kundi

Orcid: 0000-0001-5120-0887

According to our database1, Dur-e-Shahwar Kundi authored at least 25 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining.
IEEE Trans. Computers, December, 2023

2022
A High-Performance SIKE Hardware Accelerator.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs.
IEEE Trans. Emerg. Top. Comput., 2022

A High Performance SIKE Accelerator With High Frequency and Low Area-Time Product.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications.
IEEE Internet Things J., 2022

Efficient Pipelining Exploration for A High-performance CRYSTALS-Kyber Accelerator.
IACR Cryptol. ePrint Arch., 2022

Stacked Ensemble Model for Enhancing the DL based SCA.
Proceedings of the 19th International Conference on Security and Cryptography, 2022

A Lightweight and Efficient Schoolbook Polynomial Multiplier for Saber.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Horizontal Correlation Analysis without Precise Location on Schoolbook Polynomial Multiplication of Lattice-based Cryptosystem.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Stacked Ensemble Models Evaluation on DL Based SCA.
Proceedings of the E-Business and Telecommunications - 19th International Conference, 2022

Approximate Computing for Cryptography.
Proceedings of the Approximate Computing, 2022

2021
APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations.
IEEE Trans. Inf. Forensics Secur., 2021

Towards CRYSTALS-Kyber: A M-LWE Cryptoprocessor with Area-Time Trade-Off.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

High-Performance Systolic Array Montgomery Multiplier for SIKE.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
An Efficient and Parallel R-LWE Cryptoprocessor.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3.
IEEE Trans. Circuits Syst., 2020

AxMM: Area and Power Efficient Approximate Modular Multiplier for R-LWE Cryptosystem.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A Pareto-Optimal Multi-filter Architecture on FPGA for Image Processing Applications.
Circuits Syst. Signal Process., 2019

2018
Multi-resolution transforms-based hybrid feature extraction technique for differentiating glioma grades.
Int. J. Wavelets Multiresolution Inf. Process., 2018

2017
Non Sub-sampled Contourlet Transform Based Feature Extraction Technique for Differentiating Glioma Grades Using MRI Images.
Proceedings of the AI 2017: Advances in Artificial Intelligence, 2017

2016
A high performance ST-Box based unified AES encryption/decryption architecture on FPGA.
Microprocess. Microsystems, 2016

A low-power SHA-3 designs using embedded digital signal processing slice on FPGA.
Comput. Electr. Eng., 2016

2015
An efficient single unit T-box/T<sup>-1</sup>-box implementation for 128-bit AES on FPGA.
Secur. Commun. Networks, 2015

2013
Software implementation of Standard Hash Algorithm (SHA-3) Keccak on Intel core-i5 and Cavium Networks Octeon Plus embedded platform.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

2010
Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA.
Inf. Process. Lett., 2010


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