Asisa Kumar Panigrahi

Orcid: 0000-0002-9491-5310

According to our database1, Asisa Kumar Panigrahi authored at least 7 papers between 2015 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
TCAD Simulation of a 10nm n-Channel Vertical Double Gate Silicon On Insulator MOSFET for Digital Applications.
Proceedings of the 13th International Conference on Computing Communication and Networking Technologies, 2022

2016
Analysis of graphene and CNT based finned TTSV and spreaders for thermal management in 3D IC.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

Improved noise coupling performance using optimized Teflon liner with different TSV structures for 3D IC integration.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

Low temperature CMOS compatible Cu-Cu thermo-compression bonding with constantan alloy passivation for 3D IC integration.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

Noise performance improvement through optimized stacked layer of liner structure around the TSV in 3D IC.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

Novel inter layer dielectric and thermal TSV material for enhanced heat mitigation in 3-D IC.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Long term efficacy of ultra-thin Ti passivation layer for achieving low temperature, low pressure Cu-Cu Wafer-on-Wafer bonding.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015


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