Atanas N. Parashkevov

According to our database1, Atanas N. Parashkevov authored at least 7 papers between 1997 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2017
Virtualization Based Development.
Proceedings of the Concurrency, Security, and Puzzles, 2017

2006
Coverage Measurement for Software Application Testing using Partially Ordered Domains and Symbolic Trajectory Evaluation Techniques.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005
A software test program generator for verifying system-on-chips.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

2004
Coverage Measurement for Software Application Level Verification using Symbolic Trajectory Evaluation Techniques.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003
An automated method for test model generation from switch level circuits.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Automated equivalence checking of switch level circuits .
Proceedings of the 39th Design Automation Conference, 2002

1997
Space Efficient Reachability Analysis Through Use of Pseudo-Root States.
Proceedings of the Tools and Algorithms for Construction and Analysis of Systems, 1997


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