Magdy S. Abadir

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs.

[BibT_eX]

[DOI]

J. Electron. Test., 2013

Keynote 1 - VLSI 2.0: R&D Post Moore.

[BibT_eX]

[DOI]

Sani R. Nassif

Yale N. Patt

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Novel test analysis to improve structural coverage - A commercial experiment.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A pattern mining framework for inter-wafer abnormality analysis.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

Simulation knowledge extraction and reuse in constrained random processor verification.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Introduction to special section on verification challenges in the concurrent world.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

Data mining based prediction paradigm and its applications in design automation.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

An experiment of burn-in time reduction based on parametric test analysis.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Screening customer returns with multivariate test analysis.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Novel test detection to improve simulation efficiency - A commercial experiment.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

Understanding customer returns from a test perspective.

[BibT_eX]

[DOI]

LeRoy Winemberg

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Forward prediction based on wafer sort data - A case study.

[BibT_eX]

[DOI]

LeRoy Winemberg

Proceedings of the 2011 IEEE International Test Conference, 2011

Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2010

Design for reality: knowledge discovery in design and test data.

[BibT_eX]

[DOI]

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Coverage metrics for verification of concurrent SystemC designs using mutation testing.

[BibT_eX]

[DOI]

Alper Sen

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch.

[BibT_eX]

[DOI]

Nicholas Callegari

Proceedings of the 47th Design Automation Conference, 2010

2009

A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Minimizing outlier delay test cost in the presence of systematic variability.

[BibT_eX]

[DOI]

Brendon Bolin

Proceedings of the 2009 IEEE International Test Conference, 2009

TRAM: A tool for Temperature and Reliability Aware Memory Design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Validating Power ArchitectureTM Technology-Based MPSoCs Through Executable Specifications.

[BibT_eX]

[DOI]

Ekaterina Trofimova

IEEE Trans. Very Large Scale Integr. Syst., 2008

Linking Statistical Learning to Diagnosis.

[BibT_eX]

[DOI]

Pouria Bastani

IEEE Des. Test Comput., 2008

Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Predictive runtime verification of multi-processor SoCs in SystemC.

[BibT_eX]

[DOI]

Alper Sen

Vinit Ogale

Proceedings of the 45th Design Automation Conference, 2008

Statistical diagnosis of unmodeled systematic timing effects.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

A Survey of Hybrid Techniques for Functional Verification.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2007

Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2007

STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Statistical analysis and optimization of parametric delay test.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

Analyzing the risk of timing modeling based on path delay tests.

[BibT_eX]

[DOI]

Pouria Bastani

Savithri Sundareswaran

Proceedings of the 2007 IEEE International Test Conference, 2007

Maximum circuit activity estimation using pseudo-boolean satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Design-Silicon Timing Correlation A Data Mining Perspective.

[BibT_eX]

[DOI]

Pouria Bastani

Proceedings of the 44th Design Automation Conference, 2007

LEAF: A System Level Leakage-Aware Floorplanner for SoCs.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

A Trace-Driven Validation Methodology for Multi-Processor SOCS.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Extracting a Simplified View of Design Functionality Based on Vector Simulation.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software, 2006

Extracting a simplified view of design functionality via vector simulation.

[BibT_eX]

[DOI]

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Refined statistical static timing analysis through.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Floorplan driven leakage power aware IP-based SoC design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005

A methodology for validation of microprocessors using symbolic simulation.

[BibT_eX]

[DOI]

Prabhat Mishra

Nikil D. Dutt

Int. J. Embed. Syst., 2005

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Reducing Pattern Delay Variations for Screening Frequency Dependent Defects.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Recent Advances in Verification, Equivalence Checking and SAT-Solvers.

[BibT_eX]

[DOI]

Dhiraj K. Pradhan

Mauricio Varea

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Retiming Verification Using Sequential Equivalence Checking.

[BibT_eX]

[DOI]

Brian Kahne

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Post-Verification Debugging of Hierarchical Designs.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Establishing latch correspondence for embedded circuits of PowerPC microprocessors.

[BibT_eX]

[DOI]

Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Diagnosing multiple transition faults in the absence of timing information.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Choosing flows and methodologies for SoC design.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

2004

IDAP: a tool for high-level power estimation of custom array structures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A Top-Down Methodology for Microprocessor Validation.

[BibT_eX]

[DOI]

Prabhat Mishra

Nikil D. Dutt

IEEE Des. Test Comput., 2004

Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2004

Guest Editors' Introduction: The Verification and Test of Complex Digital ICs.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2004

Towards The Complete Elimination of Gate/Switch Level Simulations.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Identification of Gates for Covering all Critical Paths.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Debugging Sequential Circuits Using Boolean Satisfiability.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Fault equivalence and diagnostic test generation using ATPG.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

On path-based learning and its applications in delay test and diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Analytical models for leakage power estimation of memory array structures.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

Formal Verification Successes at Motorola.

[BibT_eX]

[DOI]

Ken Albin

John Havlicek

Formal Methods Syst. Des., 2003

Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems.

[BibT_eX]

[DOI]

Tao Feng

Kwang-Ting (Tim) Cheng

Manish Pandey

Des. Autom. Embed. Syst., 2003

Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs.

[BibT_eX]

[DOI]

Juhong Zhu

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Automated Test Model Generation from Switch Level Custom Circuits.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Logic verification based on diagnosis techniques.

[BibT_eX]

[DOI]

Alexander Smith

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

An automated method for test model generation from switch level circuits.

[BibT_eX]

[DOI]

Tim McDougall

Atanas N. Parashkevov

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Enhanced symbolic simulation for efficient verification of embedded array systems.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Design rewiring using ATPG.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Validation and Verification of Complex Digital Systems: A Practical Perspective.

[BibT_eX]

Proceedings of the 3rd Latin American Test Workshop, 2002

Efficient and Exact Diagnosis of Multiple Stuck-At Faults.

[BibT_eX]

Jiang Brandon Liu

Proceedings of the 3rd Latin American Test Workshop, 2002

On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults.

[BibT_eX]

[DOI]

Juhong Zhu

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Design Rewiring Using ATPG.

[BibT_eX]

[DOI]

Mandana Amiri

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.

[BibT_eX]

[DOI]

Ganapathy Parthasarathy

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Incremental Diagnosis and Correction of Multiple Faults and Errors.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Minimal Test for Coupling Faults in Word-Oriented Memories.

[BibT_eX]

[DOI]

Ad J. van de Goor

Alan Carlin

Proceedings of the 2002 Design, 2002

False timing path identification using ATPG techniques and delay-based information.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

Design and Development Paradigm for Industrial Formal Verification CAD Tools.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2001

Very Low Cost Testers: Opportunities and Challenges.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2001

Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor.

[BibT_eX]

[DOI]

Juhong Zhu

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

ATPG for Design Errors-Is It Possible?

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

ATPG Driven Logic Synthesis for Delay and Power Minimization.

[BibT_eX]

Ivor Ting

Proceedings of the 2nd Latin American Test Workshop, 2001

Verification and Validation of Complex Digital Systems: An Industrial Perspective.

[BibT_eX]

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation.

[BibT_eX]

[DOI]

Mrinal Bose

Elizabeth M. Rudnick

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A language formalism for verification of PowerPCTM custom memories using compositions of abstract specifications.

[BibT_eX]

[DOI]

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Full chip false timing path identification: applications to the PowerPCTM microprocessors.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation.

[BibT_eX]

[DOI]

Proceedings of the Correct Hardware Design and Verification Methods, 2001

Design rewiring based on diagnosis techniques.

[BibT_eX]

[DOI]

Ivor Ting

Proceedings of ASP-DAC 2001, 2001

2000

Oscillation Ring Delay Test for High Performance Microprocessors.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

Guest Editorial.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

Validating PowerPC Microprocessor Custom Memories.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2000

Guest Editors' Introduction: Microprocessor Test and Verification.

[BibT_eX]

Sumit Dasgupta

IEEE Des. Test Comput., 2000

Validation of PowerPC(tm) Custom Memories using Symbolic Simulation.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Design Optimization Based on Diagnosis Techniques.

[BibT_eX]

Ibrahim N. Haji

Proceedings of the 1st Latin American Test Workshop, 2000

A Quick and Inexpensive Method to Identify False Critical Paths Using ATPG Techniques: an Experiment with a PowerPC Microprocessor.

[BibT_eX]

Jayanta Batra

Proceedings of the 1st Latin American Test Workshop, 2000

A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPCTM microprocessor.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999

Experience in Validation of PowerPCTM Microprocessor Embedded Arrays.

[BibT_eX]

[DOI]

J. Electron. Test., 1999

Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Design-for-test methodology for Motorola PowerPC microprocessors.

[BibT_eX]

[DOI]

Rajesh Raina

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1998

Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays.

[BibT_eX]

[DOI]

J. Electron. Test., 1998

On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors.

[BibT_eX]

[DOI]

Arun Chandra

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation.

[BibT_eX]

[DOI]

Nari Krishnamurthy

Proceedings of the 35th Conference on Design Automation, 1998

1997

Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1997

Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die.

[BibT_eX]

[DOI]

Cynthia F. Murphy

Peter Sandborn

J. Electron. Test., 1997

Design and Test Economics-An Extra Dimension.

[BibT_eX]

Tony Ambler

IEEE Des. Test Comput., 1997

Cost-Driven Ranking of Memory Elements for Partial Intrusion.

[BibT_eX]

[DOI]

Rohit Kapur

IEEE Des. Test Comput., 1997

Microprocessor Test and Validation: Any New Avenues?

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

A New Validation Methodology Combining Test and Formal Verification for PowerPCTM Microprocessor Arrays.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

1996

PowerPCTM Array Verification Methodology using Formal Techniques.

[BibT_eX]

[DOI]

Neeta Ganguly

Manish Pandey

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1994

Multichip systems trade-off analysis tool.

[BibT_eX]

[DOI]

J. Electron. Test., 1994

High Level Test Economics Advisor (Hi-TEA).

[BibT_eX]

[DOI]

J. Electron. Test., 1994

Introduction.

[BibT_eX]

[DOI]

Tony Ambler

J. Electron. Test., 1994

Analyzing Multichip Module Testing Strategies.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1994

Efficient Algorithmic Circuit Verification Using Indexed BDDs.

[BibT_eX]

[DOI]

Proceedings of the Digest of Papers: FTCS/24, 1994

1993

AMBIANT: Automatic Generation of Behavioral Modifications for Testability.

[BibT_eX]

[DOI]

Praveen Vishakantaiah

Thomas Thomas

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992

Automatic Test Knowledge Extraction from VHDL (ATKET).

[BibT_eX]

[DOI]

Praveen Vishakantaiah

Proceedings of the 29th Design Automation Conference, 1992

1991

Partitioning Hierarchical Designs for Testability.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

An improved layout verification algorithm (LAVA).

[BibT_eX]

[DOI]

Jack Ferguson

Proceedings of the European Design Automation Conference, 1990

1989

TIGER: testability insertion guidance expert system.

[BibT_eX]

[DOI]

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988

Logic design verification via test generation.

[BibT_eX]

[DOI]

Jack Ferguson

Tom E. Kirkland

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1986

Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1986

Test Schedules for VLSI Circuits Having Built-In Test Hardware.

[BibT_eX]

[DOI]

Melvin A. Breuer

IEEE Trans. Computers, 1986

Scan Path with Look Ahead Shifting (SPLASH).

[BibT_eX]

Melvin A. Breuer

Proceedings of the Proceedings International Test Conference 1986, 1986

1985

A Knowledge-Based System for Designing Testable VLSI Chips.

[BibT_eX]

[DOI]

Melvin A. Breuer

IEEE Des. Test, 1985

Functional Test Generation for LSI Circuits Described by Binary Decision Diagrams.

[BibT_eX]

Proceedings of the Proceedings International Test Conference 1985, 1985

1984

Test generation for LSI: A case study.

[BibT_eX]

[DOI]

Proceedings of the 21st Design Automation Conference, 1984

1983

LSI Testing Techniques.

[BibT_eX]

[DOI]

IEEE Micro, 1983

Functional Testing of Semiconductor Random Access Memories.

[BibT_eX]

[DOI]