Atef Ibrahim
Orcid: 0000-0002-1115-4051
According to our database1,
Atef Ibrahim
authored at least 32 papers
between 2011 and 2022.
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Bibliography
2022
Compact Finite Field Multiplication Processor Structure for Cryptographic Algorithms in IoT Devices with Limited Resources.
Sensors, 2022
Compact modular multiplier design for strong security capabilities in resource-limited Telehealth IoT devices.
J. King Saud Univ. Comput. Inf. Sci., 2022
The Industrial Internet of Things (IIoT): An Anomaly Identification and Countermeasure Method.
J. Circuits Syst. Comput., 2022
Systolic Processor Core for Finite-Field Multiplication and Squaring in Cryptographic Processors of IoT Edge Devices.
IEEE Internet Things J., 2022
2021
J. Intell. Fuzzy Syst., 2021
A Pervasive Computational Intelligence based Cognitive Security Co-design Framework for Hype-connected Embedded Industrial IoT.
Int. J. Comput. Commun. Control, 2021
Low-space bit-serial systolic array architecture for interleaved multiplication over GF(2m).
IET Comput. Digit. Tech., 2021
Comput. Electr. Eng., 2021
2020
Unified and Scalable Digit-Serial Systolic Array for Multiplication and Division Over GF (2m).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Int. J. Comput. Commun. Control, 2020
IEEE Access, 2020
2019
IEEE Trans. Consumer Electron., 2019
Low-Complexity Scalable Architectures for Parallel Computation of Similarity Measures.
Sci. Program., 2019
Microelectron. J., 2019
Blockchain in internet-of-things: a necessity framework for security, reliability, transparency, immutability and liability.
IET Commun., 2019
Efficient parallel semi-systolic array structure for multiplication and squaring in GF(2<i><sup>m</sup></i>).
IEICE Electron. Express, 2019
Novel bit-serial semi-systolic array structure for simultaneously computing field multiplication and squaring.
IEICE Electron. Express, 2019
Implementation of High Speed and Low Area Extended Euclidean Inversion over Ternary Fields.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019
2018
IEICE Electron. Express, 2018
2017
Design Space Exploration of 2-D Processor Array Architectures for Similarity Distance Computation.
IEEE Trans. Parallel Distributed Syst., 2017
Scalable and Unified Digit-Serial Processor Array Architecture for Multiplication and Inversion Over GF( $2^{m}$ ).
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Comput. Electr. Eng., 2017
2016
Low Power Semi-systolic Architectures for Polynomial-Basis Multiplication over GF(2 m ) Using Progressive Multiplier Reduction.
J. Signal Process. Syst., 2016
Low space-complexity and low power semi-systolic multiplier architectures over GF(2<sup>m</sup>) based on irreducible trinomial.
Microprocess. Microsystems, 2016
Novel Reconfigurable Hardware Accelerator for Protein Sequence Alignment Using Smith-Waterman Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Efficient Scalable Digit-Serial Inverter Over GF( $2^{m}$ ) for Ultra-Low Power Devices.
IEEE Access, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Microelectron. J., 2015
2011
Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm.
IEEE Trans. Parallel Distributed Syst., 2011
New processor array architecture for scalable radix 8 montgomery modular multiplication algorithm.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011