Fayez Gebali

According to our database1, Fayez Gebali authored at least 75 papers between 2002 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Thermal-aware network-on-chips: Single- and cross-layered approaches.
Future Generation Comp. Syst., 2019

2018
New systolic array architecture for finite field division.
IEICE Electronic Express, 2018

Multi-Core Dataflow Design and Implementation of Secure Hash Algorithm-3.
IEEE Access, 2018

2017
Design Space Exploration of 2-D Processor Array Architectures for Similarity Distance Computation.
IEEE Trans. Parallel Distrib. Syst., 2017

Scalable and Unified Digit-Serial Processor Array Architecture for Multiplication and Inversion Over GF( $2^{m}$ ).
IEEE Trans. on Circuits and Systems, 2017

Unified systolic array architecture for finite field multiplication and inversion.
Computers & Electrical Engineering, 2017

On Time Compression Overlap-Add Technique in Linear Frequency Modulation Pulse Compression Radar Systems: Design and Performance Evaluation.
IEEE Access, 2017

Throughput analysis of point-to-multi-point hybric FSO/RF network.
Proceedings of the IEEE International Conference on Communications, 2017

Systolic design space exploration of polynomial division over GF(m2).
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016
Low Power Semi-systolic Architectures for Polynomial-Basis Multiplication over GF(2 m ) Using Progressive Multiplier Reduction.
Signal Processing Systems, 2016

Low space-complexity and low power semi-systolic multiplier architectures over GF(2m) based on irreducible trinomial.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Multi-dimensional analysis of embedded systems security.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Hardware attacks: an algebraic approach.
J. Cryptographic Engineering, 2016

Optimal Design of Dual-Hop VLC/RF Communication System With Energy Harvesting.
IEEE Communications Letters, 2016

A New Characterization of Hardware Trojans.
IEEE Access, 2016

Efficient Scalable Digit-Serial Inverter Over GF( $2^{m}$ ) for Ultra-Low Power Devices.
IEEE Access, 2016

Dual-Hop VLC/RF Transmission System with Energy Harvesting Relay under Delay Constraint.
Proceedings of the 2016 IEEE Globecom Workshops, Washington, DC, USA, December 4-8, 2016, 2016

Design and implementation of BPSK MODEM for IEEE 802.15.4/ZigBee devices.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

Hardware Covert Attacks and Countermeasures.
Proceedings of the 30th IEEE International Conference on Advanced Information Networking and Applications, 2016

2015
Systolic Array Architectures for Sunar-Koç Optimal Normal Basis Type II Multiplier.
IEEE Trans. VLSI Syst., 2015

Efficient Scalable Serial Multiplier Over GF(2m) Based on Trinomial.
IEEE Trans. VLSI Syst., 2015

Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders.
Microelectronics Journal, 2015

Outage Analysis of Practical FSO/RF Hybrid System With Adaptive Combining.
IEEE Communications Letters, 2015

Joint Adaptive Modulation and Combining for Hybrid FSO/RF Systems.
Proceedings of the IEEE International Conference on Ubiquitous Wireless Broadband, 2015

Outage Performance of Hybrid FSO/RF System with Low-Complexity Power Adaptation.
Proceedings of the 2015 IEEE Globecom Workshops, San Diego, CA, USA, December 6-10, 2015, 2015

2014
Reliability analysis and fault tolerance for hypercube multi-computer networks.
Inf. Sci., 2014

SMARTs: A Tool to Simulate and Analyze the Performance of Real-time Multi-core Systems.
Proceedings of the 9th International Conference on Future Networks and Communications (FNC'14) / The 11th International Conference on Mobile Systems and Pervasive Computing (MobiSPC'14) / Affiliated Workshops, 2014

Power-aware Mapping for 3D-NoC Designs Using Genetic Algorithms.
Proceedings of the 9th International Conference on Future Networks and Communications (FNC'14) / The 11th International Conference on Mobile Systems and Pervasive Computing (MobiSPC'14) / Affiliated Workshops, 2014

2013
Power consumption of 3D networks-on-chips: Modeling and optimization.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Unified multi-objective mapping and architecture customisation of networks-on-chip.
IET Computers & Digital Techniques, 2013

2012
DSDMAC: Dual Sensing Directional MAC Protocol for Ad Hoc Networks with Directional Antennas.
IEEE Trans. Vehicular Technology, 2012

GPS Waypoint Application.
Proceedings of the 2012 Seventh International Conference on Broadband, 2012

DominoMAC: A Wireless Sensor Networks Medium Access Protocol.
Proceedings of the 2012 Seventh International Conference on Broadband, 2012

2011
Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm.
IEEE Trans. Parallel Distrib. Syst., 2011

Improving Networks-on-Chip performability: A topology-based approach.
I. J. Circuit Theory and Applications, 2011

New processor array architecture for scalable radix 8 montgomery modular multiplication algorithm.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

Performance-optimized FPGA implementation for the flexible triangle search block-based motion estimation algorithm.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

Finite Field Multiplication Using Reordered Normal Basis Multiplier.
Proceedings of the 2011 International Conference on Broadband, 2011

2010
Enhanced Busy-Tone-Assisted MAC Protocol for Wireless Ad Hoc Networks.
Proceedings of the 72nd IEEE Vehicular Technology Conference, 2010

Multi-objective optimization of NoC standard architectures using Genetic Algorithms.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2010

Multi-objective optimization for Networks-on-Chip architectures using Genetic Algorithms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Networks-on-chip topology optimization subject to power, delay, and reliability constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Power optimization for application-specific networks-on-chips: A topology-based approach.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

A spam rejection scheme during SMTP sessions based on layer-3 e-mail classification.
J. Network and Computer Applications, 2009

Targeting spam control on middleboxes: Spam detection based on layer-3 e-mail content classification.
Computer Networks, 2009

Cross-Layer Modeling of Wireless Ad Hoc Networks in the Presence of Channel Noise.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

Modeling the Throughput and Delay in Wireless Multihop Ad Hoc Networks.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

A Multi-channel QoS Model for Random Access Systems.
Proceedings of the 7th Annual Conference on Communication Networks and Services Research, 2009

Analytical modelling and performance analysis forwireless ad-hoc networks using four-way handshaking mechanism.
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

Cross-layer analysis of wireless LANS: Backoff strategies and error control.
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

2008
Corrections to "Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit" [Dec 07 2683-2695].
IEEE Trans. on Circuits and Systems, 2008

Prioritized e-mail servicing to reduce non-spam delay and loss: A performance analysis.
Int. Journal of Network Management, 2008

Binary LNS-based naive Bayes inference engine for spam control: noise analysis and FPGA implementation.
IET Computers & Digital Techniques, 2008

Design Space Exploration of a Reconfigurable HMAC-Hash Unit.
Journal of Research and Practice in Information Technology, 2008

Backoff Strategies in Hiperlan2 with Error Control Protocol.
Proceedings of the 68th IEEE Vehicular Technology Conference, 2008

Quality of service support and backoff strategies in wireless networks with error control protocol.
Proceedings of the 3rd ACM Workshop on Performance Monitoring and Measurement of Heterogeneous Wireless and Wired Networks, 2008

Quality of service support in wireless local area network with error control protocol.
Proceedings of the LCN 2008, 2008

Power-aware topology optimization for networks-on-chips.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Application-specific networks-on-chip topology customization using network partitioning.
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008

2007
Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit.
IEEE Trans. on Circuits and Systems, 2007

Queue Modeling and Implementation for Networks-on-Chip Routers.
Journal of Circuits, Systems, and Computers, 2007

Modeling and Implementation of an Output-Queuing Router for Networks-on-Chips.
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007

2006
Processor Array Architectures for Deep Packet Classification.
IEEE Trans. Parallel Distrib. Syst., 2006

A hierarchical design methodology for full-search block matching motion estimation.
Multidim. Syst. Sign. Process., 2006

Communication Networks Performance of collaborative codes in CSMA/CD environment.
European Transactions on Telecommunications, 2006

An FPGA implementation of the flexible triangle search algorithm for block based motion estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Binary LNS-based naive Bayes hardware classifier for spam control.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Distributed Layer-3 E-Mail Classification for Spam Control.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005
Markov chain analysis of collaborative codes in random multi access communication systems.
Computer Communications, 2005

Systolic Array-Based String Matching Unit for Spam Blocking.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

An FPGA Design of a Unified Hash Engine for IPSec Authentication.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

2004
A fast string search algorithm for deep packet classification.
Computer Communications, 2004

A new analytical model for computing blocking probability in optical burst switching networks.
Proceedings of the 9th IEEE Symposium on Computers and Communications (ISCC 2006), June 28, 2004

Analytical evaluation of blocking probability in optical burst switching networks.
Proceedings of IEEE International Conference on Communications, 2004

2002
The JAFARDD processor: a Java architecture based on a Folding Algorithm, with Reservation stations, Dynamic translation, and Dual processing.
IEEE Trans. Consumer Electronics, 2002


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