Avijit Chakraborty

Orcid: 0000-0002-1875-4957

According to our database1, Avijit Chakraborty authored at least 4 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Topological Heuristics for Scan Test Overhead Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

2020
Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2018
Intel nGraph: An Intermediate Representation, Compiler, and Executor for Deep Learning.
CoRR, 2018

2015
Optimizing VMIN of ROM Arrays Without Loss of Noise Margin.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015


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