D. M. H. Walker

According to our database, D. M. H. Walker authored at least 85 papers between 1986 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Topological Heuristics for Scan Test Overhead Reduction.

Avijit Chakraborty, Duncan M. Hank Walker

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

2020

Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits.

Avijit Chakraborty, D. M. H. Walker

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2017

Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra.

Prasenjit Biswas, D. M. H. Walker

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2015

Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise.

Tengteng Zhang, Yukun Gao, D. M. H. Walker

J. Electron. Test., 2015

Pseudo Functional Path Delay Test through Embedded Memories.

Yukun Gao, Tengteng Zhang, Punj Pokharel, Swati Chakraborty, D. M. H. Walker

J. Electron. Test., 2015

At-Speed Path Delay Test.

Swati Chakraborty, Duncan M. Hank Walker

Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

Optimizing VMIN of ROM Arrays Without Loss of Noise Margin.

Avijit Chakraborty, D. M. H. Walker

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Impact of test compression on power supply noise control.

Tengteng Zhang, D. M. H. Walker

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

Improved power supply noise control for pseudo functional test.

Tengteng Zhang, Duncan M. Hank Walker

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation.

Kun Bian, D. M. H. Walker, Sunil P. Khatri

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise.

Tengteng Zhang, Yukun Gao, D. M. H. Walker

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

Delay Test of Embedded Memories.

Yukun Gao, Tengteng Zhang, Swati Chakraborty, D. M. H. Walker

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

K Longest Paths.

Duncan M. Hank Walker

Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014

2013

Power supply noise control in pseudo functional test.

Tengteng Zhang, Duncan M. Hank Walker

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Mixed structural-functional path delay test generation and compaction.

Kun Bian, D. M. H. Walker, Sunil P. Khatri, Shayak Lahiri

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

Maximizing crosstalk-induced slowdown during path delay test.

Dibakar Gope, D. M. H. Walker

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011

Levelized low cost delay test compaction considering IR-drop induced power supply noise.

Zhongwei Jiang, Zheng Wang, Jing Wang, D. M. H. Walker

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2009

Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric.

Zheng Wang, Duncan M. Hank Walker

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Challenges in Delay Testing of Integrated Circuits.

D. M. H. Walker

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations.

Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker

Integr., 2008

Dynamic Compaction for High Quality Delay Test.

Zheng Wang, D. M. H. Walker

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

2007

Modeling Power Supply Noise in Delay Testing.

Jing Wang, Duncan M. Hank Walker, Xiang Lu, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul J. A. M. van de Wiel, Stefan Eichenberger

IEEE Des. Test Comput., 2007

2006

Estimation of fault-free leakage current using wafer-level spatial information.

Sagar S. Sabade, D. M. H. Walker

IEEE Trans. Very Large Scale Integr. Syst., 2006

Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in {VLSI} Circuits.

Hyun Sung Kim, D. M. H. Walker

Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

Power Supply Noise in Delay Testing.

Jing Wang, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger

Proceedings of the 2006 IEEE International Test Conference, 2006

Comparison of Delay Tests on Silicon.

Wangqi Qiu, D. M. H. Walker, Neil Simpson, Divya Reddy, Anthony Moore

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Longest-path selection for delay test under process variation.

Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

IC Outlier Identification Using Multiple Test Metrics.

Sagar S. Sabade, Duncan M. Hank Walker

IEEE Des. Test Comput., 2005

Static Compaction of Delay Tests Considering Power Supply Noise.

Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Is IDDQ Test of Microprocessors Feasible?

Bin Xue, D. M. H. Walker

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Reliable energy efficient routing in wireless sensor networks.

Eunjae Jung, Duncan M. Hank Walker

Proceedings of the IEEE 2nd International Conference on Mobile Adhoc and Sensor Systems, 2005

I_DDQ test using built-in current sensing of supply line voltage drop.

Bin Xue, D. M. H. Walker

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A vector-based approach for power supply noise analysis in test compaction.

Jing Wang, Ziding Yue, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits.

Lei Wu, D. M. H. Walker

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004

I_DDX-based test methods: A survey.

Sagar S. Sabade, D. M. H. Walker

ACM Trans. Design Autom. Electr. Syst., 2004

I_DDQ data analysis using neighbor current ratios.

Sagar S. Sabade, D. M. H. Walker

J. Syst. Archit., 2004

On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set.

Sagar S. Sabade, D. M. H. Walker

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

A Statistical Fault Coverage Metric for Realistic Path Delay Faults.

Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests.

Sagar S. Sabade, D. M. H. Walker

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide.

Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits.

Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

PARADE: PARAmetric Delay Evaluation under Process Variation.

Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2003

A circuit level fault model for resistive bridges.

Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker

ACM Trans. Design Autom. Electr. Syst., 2003

Use of Multiple IDDQ Test Metrics for Outlier Identification.

Sagar S. Sabade, D. M. H. Walker

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A Circuit Level Fault Model for Resistive Opens and Bridges.

Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification.

Sagar S. Sabade, D. M. H. Walker

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Testing the Path Delay Faults of ISCAS85 Circuit c6288.

Wangqi Qiu, D. M. H. Walker

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit.

Wangqi Qiu, D. M. H. Walker

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

CROWNE: Current Ratio Outliers with Neighbor Estimator.

Sagar S. Sabade, D. M. H. Walker

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

CodSim -- A Combined Delay Fault Simulator.

Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors.

Abhijit Prasad, D. M. H. Walker

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002

IDDQ Test: Will It Survive the DSM Challenge?

Sagar S. Sabade, D. M. H. Walker

IEEE Des. Test Comput., 2002

Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction.

Sagar S. Sabade, D. M. H. Walker

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting.

Sagar S. Sabade, D. M. H. Walker

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis.

Sagar S. Sabade, D. M. H. Walker

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001

FedEx - a fast bridging fault extractor.

Zoran Stanojevic, D. M. H. Walker

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Improved wafer-level spatial analysis for I_DDQ limit setting.

Sagar S. Sabade, D. M. H. Walker

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A practical built-in current sensor for I_DDQ testing.

Hoki Kim, D. M. H. Walker, David Colby

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

An efficient solution to the storage correspondence problem for large sequential circuits.

Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee

Proceedings of ASP-DAC 2001, 2001

2000

PROBE: A PPSFP Simulator for Resistive Bridging Faults.

Chul Young Lee, D. M. H. Walker

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation.

Byungwoo Choi, D. M. H. Walker

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Computer-aided fault to defect mapping (CAFDM) for defect diagnosis.

Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999

Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits.

Debashis Nayak, D. M. H. Walker

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Design for Yield and Reliability is MORE Important Than DFT.

D. M. H. Walker

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Resistive bridge fault modeling, simulation and test generation.

Vijay R. Sar-Dessai, D. M. H. Walker

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs.

Lan Zhao, D. M. H. Walker, Fabrizio Lombardi

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.

Lan Zhao, D. M. H. Walker, Fabrizio Lombardi

IEEE Trans. Computers, 1998

Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ.

Lan Zhao, D. M. H. Walker, Fabrizio Lombardi

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Bridging Fault Detection in FPGA Interconnects Using <i>I_DDQ</i>.

Lan Zhao, D. M. H. Walker, Fabrizio Lombardi

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Accurate Fault Modeling and Fault Simulation of Resistive Bridges.

Vijay R. Sar-Dessai, D. M. H. Walker

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1996

Optimal voltage testing for physically-based faults.

Yuyun Liao, D. M. H. Walker

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Improvement of SRAM-based failure analysis using calibrated Iddq testing.

Hari Balachandran, D. M. H. Walker

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Test Generation for Global Delay Faults.

G. M. Luong, D. M. H. Walker

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages.

Yuyun Liao, D. M. H. Walker

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Fatal Fault Probability Prediction for Array Based Designs.

Dinesh D. Gaitonde, Wojciech Maly, D. M. H. Walker

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995

IC Performance Prediction System.

V. Ramakrishnan, D. M. H. Walker

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Yiel Learning via Functional Test Data.

Young-Jun Kwon, D. M. H. Walker

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Accurate yield estimation of circuits with redundancy.

Dinesh D. Gaitonde, D. M. H. Walker, Wojciech Maly

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994

Semiconductor wafer representation for TCAD.

Martin D. Giles, Duane S. Boning, Goodwin R. Chin, Walter C. Dietrich Jr., Michael S. Karasick, Mark E. Law, Purnendu K. Mozumder, Lee R. Nackman, V. T. Rajan, Duncan M. Hank Walker, Robert H. Wang, Alexander S. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1993

The CDB/HCDB semiconductor wafer representation server.

D. M. H. Walker, Chris S. Kellen, David M. Svoboda, Andrzej J. Strojwas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Estimation of reject ratio in testing of combinatorial circuits.

Dinesh D. Gaitonde, Jitendra Khare, D. M. H. Walker, Wojciech P. Maly

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Test quality and yield analysis using the DEFAM defect to fault mapper.

Dinesh D. Gaitonde, Duncan M. Hank Walker

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1991

A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator.

D. M. H. Walker, Chris S. Kellen, Andrzej J. Strojwas

Proceedings of the 28th Design Automation Conference, 1991

1990

DVLASIC: catastrophic fault yield simulation in a distributed processing environment.

Duncan M. Hank Walker, D. S. Nydick

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

1986

VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits.

D. M. H. Walker, Stephen W. Director

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986