B. Chung

According to our database, B. Chung authored at least 4 papers between 2005 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application.

B. Chung, J. B. Kuo

Integr., 2008

2006

Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique.

B. Chung, J. B. Kuo

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology.

B. Chung, J. B. Kuo

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Development and testing of a cross-sectional area measurement tool for evaluating vein size.

Brian D. Davison, K. Yeshwant, Ron Kikinis, J. Rolnick, Kelly H. Zou, B. Chung, E. K. Yucel

Comput. Biol. Medicine, 2005