J. B. Kuo

According to our database1, J. B. Kuo
  • authored at least 9 papers between 2002 and 2014.
  • has a "Dijkstra number"2 of five.

Timeline

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Links

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Bibliography

2014
Parasitic BJT versus DIBL: Floating-body-related subthreshold characteristics of SOI NMOS device.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuits.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2010
Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect.
Microelectronics Reliability, 2010

2008
Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application.
Integration, 2008

2006
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2002
0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


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