B. Srinivasu

According to our database, B. Srinivasu authored at least 12 papers between 2017 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2026

Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication.

Pragun Jaswal, L. Hemanth Krishna, B. Srinivasu

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

2025

High-Performance Gemmini-Based Matrix Multiplication Accelerator for Deep Learning Workloads.

Anurag Sharma, L. Hemanth Krishna, B. Srinivasu

IEEE Trans. Very Large Scale Integr. Syst., December, 2025

Low Complexity Three's Complement Parallel Multiplier Using Special Operators of Ternary Logic.

L. Hemanth Krishna, B. Srinivasu, K. Sridharan

IEEE Trans. Circuits Syst. II Express Briefs, November, 2025

Low Power Approximate Multiplier Architecture for Deep Neural Networks.

Pragun Jaswal, L. Hemanth Krishna, B. Srinivasu

CoRR, September, 2025

Advancing Neural Network Performance with Probabilistic Computing for ReLU Function.

Amit Singh, Amit Kumar Jangid, B. Srinivasu

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

MAGIC-Based High-Speed Adders for in-Memory Computing Using Memristors.

Shri Janani Senthil, B. Srinivasu

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2024

Energy Efficient Memristor-Based Subtractors and Comparator for In-Memory Computing in MAGIC.

Nandit Kaushik, B. Srinivasu

IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

Approximate Ternary Matrix Multiplication for Image Processing and Neural Networks.

L. Hemanth Krishna, B. Srinivasu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

2023

Memristor-based High Speed and Area Efficient Comparators in IMPLY Logic.

Nandit Kaushik, B. Srinivasu

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2022

High Performance Ternary Full Adder in CNFET-Memristor Logic Technology.

Panasa Srikanth, B. Srinivasu

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2018

CoLPUF : A Novel Configurable LFSR-based PUF.

B. Srinivasu, Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies.

B. Srinivasu, K. Sridharan

IEEE Trans. Circuits Syst. I Regul. Pap., 2017