Anupam Chattopadhyay

Romain Poussier

IACR Cryptol. ePrint Arch., 2020

On Exploiting Message Leakage in (few) NIST PQC Candidates for Practical Message Recovery and Key Recovery Attacks.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Drop by Drop you break the rock - Exploiting generic vulnerabilities in Lattice-based PKE/KEMs using EM-based Physical Attacks.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Preliminary Hardware Benchmarking of a Group of Round 2 NIST Lightweight AEAD Candidates.

[BibT_eX]

[DOI]

Mustafa Khairallah

Thomas Peyrin

IACR Cryptol. ePrint Arch., 2020

Fault Location Identification By Machine Learning.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

A Novel Duplication Based Countermeasure To Statistical Ineffective Fault Analysis.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks (Extended Version).

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Spatially Correlated Patterns in Adversarial Images.

[BibT_eX]

[DOI]

Lionell Yip En Zhi

Bryan Tan Bing Xing

Siti Rawaidah Binte Mohammad Muzaki

CoRR, 2020

RAPPER: Ransomware Prevention via Performance Counters.

[BibT_eX]

[DOI]

CoRR, 2020

A Brain-Computer Interface Framework Based on Compressive Sensing and Deep Learning.

[BibT_eX]

[DOI]

Ritu Ranjan Shrivastwa

IEEE Consumer Electron. Mag., 2020

Identification and utilization of copy number information for correcting Hi-C contact map of cancer cell lines.

[BibT_eX]

[DOI]

Ahmed Ibrahim S. Khalil

Amartya Sanyal

BMC Bioinform., 2020

Hierarchical discovery of large-scale and focal copy number alterations in low-coverage cancer genomes.

[BibT_eX]

[DOI]

Ahmed Ibrahim S. Khalil

Costerwell Khyriem

Amartya Sanyal

BMC Bioinform., 2020

Efficient Quantum Circuits for Square-Root and Inverse Square-Root.

[BibT_eX]

[DOI]

Srijit Dutta

Yaswanth Tavva

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Re-markable: Stealing Watermarked Neural Networks Through Synthesis.

[BibT_eX]

[DOI]

Chua Sheng Yang Viroy

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2020

Secure Your SoC: Building System-an-Chip Designs for Security.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Cyber Security Protocol for Secure Traffic Monitoring Systems using PUF-based Key Management.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

Authentication Protocol for Secure Automotive Systems: Benchmarking Post-Quantum Cryptography.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Enabling Efficient Mapping of XMG-Synthesized Networks to Spintronic Hardware.

[BibT_eX]

[DOI]

Suman Deb

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Deploy-able Privacy Preserving Collaborative ML.

[BibT_eX]

[DOI]

Ritabrata Maiti

Proceedings of the 40th IEEE International Conference on Distributed Computing Systems, 2020

CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Noise Resilient Compilation Policies for Quantum Approximate Optimization Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Post-Quantum Secure Boot.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Security is an architectural design constraint.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2019

Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures.

[BibT_eX]

[DOI]

Chandan Bandyopadhyay

Rakesh Das

IET Comput. Digit. Tech., 2019

Generic Side-channel attacks on CCA-secure lattice-based PKE and KEM schemes.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

Exploiting Determinism in Lattice-based Signatures - Practical Fault Attacks on pqm4 Implementations of NIST candidates.

[BibT_eX]

[DOI]

Mahabir Prasad Jhanwar

James Howe

IACR Cryptol. ePrint Arch., 2019

Improving Speed of Dilithium's Signing Procedure.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

On Misuse of Nonce-Misuse Resistance: Adapting Differential Fault Attacks on (few) CAESAR Winners.

[BibT_eX]

[DOI]

Mustafa Khairallah

IACR Cryptol. ePrint Arch., 2019

SPQCop: Side-channel protected Post-Quantum Cryptoprocessor.

[BibT_eX]

[DOI]

Arpan Jati

Naina Gupta

Somitra Kumar Sanadhya

IACR Cryptol. ePrint Arch., 2019

Mind the Portability: A Warriors Guide through Realistic Profiled Side-channel Analysis.

[BibT_eX]

[DOI]

Ritu Ranjan Shrivastwa

IACR Cryptol. ePrint Arch., 2019

The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm.

[BibT_eX]

[DOI]

CoRR, 2019

New techniques for fault-tolerant decomposition of Multi-Controlled Toffoli gate.

[BibT_eX]

[DOI]

Laxmidhar Biswal

CoRR, 2019

An iterative method for linear decomposition of index generating functions.

[BibT_eX]

[DOI]

Samir Hodzic

Enes Pasalic

Owen Noel Newton Fernando

Cryptogr. Commun., 2019

La Petite Fee Cosmo.

[BibT_eX]

[DOI]

Vinayak Teoh Kannappan

Xavier Tan

Jeffrey Yan Jack Hong

Hock Soon Seah

Proceedings of the 17th International Conference on Virtual-Reality Continuum and its Applications in Industry, 2019

SoCINT: Resilient System-on-Chip via Dynamic Intrusion Detection.

[BibT_eX]

[DOI]

Amr Sayed-Ahmed

Jawad Haj-Yahya

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Applying Modified Householder Transform to Kalman Filter.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Optimizing Quantum Circuits for Modular Exponentiation.

[BibT_eX]

[DOI]

Rakesh Das

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

ITUS: A Secure RISC-V System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

LIGHTER-R: Optimized Reversible Circuit Implementation For SBoxes.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Accelerating Binary-Matrix Multiplication on FPGA.

[BibT_eX]

[DOI]

Ricardo Jack Liwongan

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

iMACE: In-Memory Acceleration of Classic McEliece Encoder.

[BibT_eX]

[DOI]

Karthikeyan Nagarajan

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Lightweight Secure-Boot Architecture for RISC-V System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Reversible Pebble Games for Reducing Qubits in Hierarchical Quantum Circuit Synthesis.

[BibT_eX]

[DOI]

Mohammad Nasim Imtiaz Khan

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing.

[BibT_eX]

[DOI]

Karthikeyan Nagarajan

Sina Sayyah Ensan

Swaroop Ghosh

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Spintronic Device-Structure for Low-Energy XOR Logic using Domain Wall Motion.

[BibT_eX]

[DOI]

Suman Deb

Akhilesh Anilkumar Siddhanti

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Analysis of the Strict Avalanche Criterion in Variants of Arbiter-Based Physically Unclonable Functions.

[BibT_eX]

[DOI]

Proceedings of the Progress in Cryptology - INDOCRYPT 2019, 2019

Curse of Dimensionality in Adversarial Examples.

[BibT_eX]

[DOI]

Sourav Sen Gupta

Michael Kasper

Proceedings of the International Joint Conference on Neural Networks, 2019

MUQUT: Multi-Constraint Quantum Circuit Mapping on NISQ Computers: Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars.

[BibT_eX]

[DOI]

Valerio Tenace

Roberto Giorgio Rizzo

Owen Noel Newton Fernando

Andrea Calimera

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

La Petite Fee Cosmo: Learning Data Structures Through Game-Based Learning.

[BibT_eX]

[DOI]

Vinayak Teoh Kannappan

Xavier Tan

Jeffrey Yan Jack Hong

Hock Soon Seah

Hui En Lye

Proceedings of the 2019 International Conference on Cyberworlds, 2019

Number "Not Used" Once - Practical Fault Attack on pqm4 Implementations of NIST Candidates.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2019

Recruiting Fault Tolerance Techniques for Microprocessor Security.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2018

Toward Threat of Implementation Attacks on Substation Security: Case Study on Fault Detection and Isolation.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Informatics, 2018

Secure and Lightweight Compressive Sensing Using Stream Cipher.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Domain Wall Motion-Based Dual-Threshold Activation Unit for Low-Power Classification of Non-Linearly Separable Functions.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2018

Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things.

[BibT_eX]

[DOI]

Andreas Burg

Proc. IEEE, 2018

A template-based technique for efficient Clifford+T-based quantum circuit implementation.

[BibT_eX]

[DOI]

Laxmidhar Biswal

Rakesh Das

Chandan Bandyopadhyay

Microelectron. J., 2018

Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2018

TriviA and uTriviA: two fast and secure authenticated encryption schemes.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2018

Side-channel Assisted Existential Forgery Attack on Dilithium - A NIST PQC candidate.

[BibT_eX]

[DOI]

Mahabir Prasad Jhanwar

James Howe

IACR Cryptol. ePrint Arch., 2018

Number "Not" Used Once - Key Recovery Fault Attacks on LWE Based Lattice Cryptographic Schemes.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2018

Certificate Transparency Using Blockchain.

[BibT_eX]

[DOI]

D. S. V. Madala

Mahabir Prasad Jhanwar

IACR Cryptol. ePrint Arch., 2018

On Hardware Implementation of Tang-Maitra Boolean Functions.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2018

Autonomous Vehicle: Security by Design.

[BibT_eX]

[DOI]

CoRR, 2018

Adversarial Attacks and Defences: A Survey.

[BibT_eX]

[DOI]

CoRR, 2018

Quantum Circuits for Toom-Cook Multiplication.

[BibT_eX]

[DOI]

Srijit Dutta

CoRR, 2018

Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization.

[BibT_eX]

[DOI]

CoRR, 2018

RAPPER: Ransomware Prevention via Performance Counters.

[BibT_eX]

[DOI]

CoRR, 2018

Floating Point Multiplication Mapping on ReRAM Based In-memory Computing Architecture.

[BibT_eX]

[DOI]

Tarun Vatwani

Arko Dutt

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Accelerating Hash Computations Through Efficient Instruction-Set Customisation.

[BibT_eX]

[DOI]

Mayuran Sivanesan

Bajaj Ronak

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Security Vulnerabilities of Unmanned Aerial Vehicles and Countermeasures: An Experimental Study.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor.

[BibT_eX]

[DOI]

Ming Ming Wong

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code.

[BibT_eX]

[DOI]

Swagata Mandal

Yaswanth Tavva

Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

ReRAM-based In-Memory Computation of Galois Field arithmetic.

[BibT_eX]

[DOI]

Swagata Mandal

Yaswanth Tavva

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Crack me if you can: hardware acceleration bridging the gap between practical and theoretical cryptanalysis?: a Survey.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

A Blockchain Framework for Insurance Processes.

[BibT_eX]

[DOI]

Proceedings of the 9th IFIP International Conference on New Technologies, 2018

A Security Model for Intelligent Vehicles and Smart Traffic Infrastructure.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Intelligent Vehicles Symposium, 2018

BLIC: A Blockchain Protocol for Manufacturing and Supply Chain Management of ICS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2018

An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine Learning.

[BibT_eX]

[DOI]

Ritu Ranjan Shrivastwa

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

PPAP and iPPAP: PLL-Based Protection Against Physical Attacks.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Hardware-Efficient Implementation of CLOC for On-chip Authenticated Encryption.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Synthesis, Technology Mapping and Optimization for Emerging Technologies.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Lightweight ASIC Implementation of AEGIS-128.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Synthesis of Multi-valued Literal Using Lukasiewicz Logic.

[BibT_eX]

[DOI]

Anmol Prakash Surhonne

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

A New High Throughput and Area Efficient SHA-3 Implementation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Efficient and Lightweight Quantized Compressive Sensing using μ-Law.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Efficient Hardware Accelerator for NORX Authenticated Encryption.

[BibT_eX]

[DOI]

Sachin Kumar

Jawad Haj-Yahya

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

SMARTS: secure memory assurance of RISC-V trusted SoC.

[BibT_eX]

[DOI]

Ming Ming Wong

Jawad Haj-Yahya

Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

Domain Wall Motion-based XOR-like Activation Unit With A Programmable Threshold.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

Logic-In-Memory Architecture For Min/Max Search.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

DFARPA: Differential fault attack resistant physical design automation.

[BibT_eX]

[DOI]

Rajat Subhra Chakraborty

Debdeep Mukhopadhyay

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Technology-aware logic synthesis for ReRAM based in-memory computing.

[BibT_eX]

[DOI]

Luca G. Amarù

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

CoLPUF : A Novel Configurable LFSR-based PUF.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Secure and Tamper-resilient Distributed Ledger for Data Aggregation in Autonomous Vehicles.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

MAMI: Majority and Multi-Input Logic on Memristive Crossbar Array.

[BibT_eX]

[DOI]

Arko Dutt

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

RC4-AccSuite: A Hardware Acceleration Suite for RC4-Like Stream Ciphers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Hardware Architectures for Embedded Speaker Recognition Applications: A Survey.

[BibT_eX]

[DOI]

Hasna Bouraoui

Chadlia Jerad

Nejib Ben Hadj-Alouane

ACM Trans. Embed. Comput. Syst., 2017

Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design.

[BibT_eX]

[DOI]

Parallel Process. Lett., 2017

Efficient complementary resistive switch-based crossbar array Booth multiplier.

[BibT_eX]

[DOI]

Anne Siemon

Eike Linn

Microelectron. J., 2017

Attacks in Reality: the Limits of Concurrent Error Detection Codes Against Laser Fault Injection.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2017

Efficient implementation of generalized Maiorana-McFarland class of cryptographic functions.

[BibT_eX]

[DOI]

Enes Pasalic

WeiGuo Zhang

J. Cryptogr. Eng., 2017

Differential Fault Attack on Grain v1, ACORN v3 and Lizard.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

A Practical Fault Attack on ARX-like Ciphers with a Case Study on ChaCha20.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

A Comprehensive Performance Analysis of Hardware Implementations of CAESAR Candidates.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

Looting the LUTs : FPGA Optimization of AES and AES-like Ciphers for Authenticated Encryption.

[BibT_eX]

[DOI]

Mustafa Khairallah

Thomas Peyrin

IACR Cryptol. ePrint Arch., 2017

An analysis of root functions - A subclass of the Impossible Class of Faulty Functions (ICFF).

[BibT_eX]

[DOI]

Enes Pasalic

Debabani Chowdhury

Discret. Appl. Math., 2017

Depth-Optimal Quantum Circuit Placement for Arbitrary Topologies.

[BibT_eX]

[DOI]

CoRR, 2017

Storages Are Not Forever.

[BibT_eX]

[DOI]

Cogn. Comput., 2017

Efficient Binary Basic Linear Algebra Operations on ReRAM Crossbar Arrays.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Survey of secure processors.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Automatic Test Pattern Generation for Multiple Missing Gate Faults in Reversible Circuits - Work in Progress Report.

[BibT_eX]

[DOI]

Anmol Prakash Surhonne

Robert Wille

Proceedings of the Reversible Computation - 9th International Conference, 2017

Designing Parity Preserving Reversible Circuits.

[BibT_eX]

[DOI]

Chander Chandak

Proceedings of the Reversible Computation - 9th International Conference, 2017

SHA-3 implementation using ReRAM based in-memory computing architecture.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Security of autonomous vehicle as a cyber-physical system.

[BibT_eX]

[DOI]

Mohammad Nasim Imtiaz Khan

Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

Side-Channel Attack on STTRAM Based Cache for Cryptographic Application.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Secure Cyber-Physical Systems: Current trends, tools and open research problems.

[BibT_eX]

[DOI]

Alok Prakash

Muhammad Shafique

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

ReVAMP: ReRAM based VLIW architecture for in-memory computing.

[BibT_eX]

[DOI]

Rajeswari Devadoss

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A systematic security analysis of real-time cyber-physical systems.

[BibT_eX]

[DOI]

Arvind Easwaran

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Area-constrained technology mapping for in-memory computing using ReRAM devices.

[BibT_eX]

[DOI]

Arvind Easwaran

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

RunStream: A High-Level Rapid Prototyping Framework for Stream Ciphers.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2016

Three Snakes in One Hole: The First Systematic Hardware Accelerator Design for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

A Sound and Complete Axiomatization of Majority-n Logic.

[BibT_eX]

[DOI]

Luca Gaetano Amarù

Giovanni De Micheli

IEEE Trans. Computers, 2016

RunFein: a rapid prototyping framework for Feistel and SPN-based block ciphers.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2016

Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design.

[BibT_eX]

[DOI]

CoRR, 2016

Ancilla-free Reversible Logic Synthesis via Sorting.

[BibT_eX]

[DOI]

Sharif Md Khairul Hossain

CoRR, 2016

Reversible Logic Circuit Complexity Analysis via Functional Decomposition.

[BibT_eX]

[DOI]

Anubhab Baksi

CoRR, 2016

Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays.

[BibT_eX]

[DOI]

Farhad Merchant

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Hardware Accelerator for Stream Cipher Spritz.

[BibT_eX]

[DOI]

Proceedings of the 13th International Joint Conference on e-Business and Telecommunications (ICETE 2016), 2016

From reversible logic to quantum circuits: Logic design for an emerging technology.

[BibT_eX]

[DOI]

Robert Wille

Rolf Drechsler

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Racetrack memory-based encoder/decoder for low-power interconnect architectures.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Efficient implementation of multiplexer and priority multiplexer using 1S1R ReRAM crossbar arrays.

[BibT_eX]

[DOI]

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Energy Optimization of Racetrack Memory-Based SIMON Block Cipher.

[BibT_eX]

[DOI]

Suman Deb

Hao Yu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation.

[BibT_eX]

[DOI]

Anubhab Baksi

Thambipillai Srikanthan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs.

[BibT_eX]

[DOI]

Alessandro Littarru

Emmanuel Ikechukwu Ugwu

Shazia Kanwal

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits.

[BibT_eX]

[DOI]

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Notes on Majority Boolean Algebra.

[BibT_eX]

[DOI]

Luca Gaetano Amarù

Mathias Soeken

Giovanni De Micheli

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation.

[BibT_eX]

[DOI]

Laxmidhar Biswal

Chandan Bandyopadhyay

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Modified projected Landweber method for Compressive-Sensing reconstruction of images with non-orthogonal matrices.

[BibT_eX]

[DOI]

Thambipillai Srikanthan

Proceedings of the International Symposium on Integrated Circuits, 2016

Low-quantum cost circuit constructions for adder and symmetric Boolean functions.

[BibT_eX]

[DOI]

Anubhab Baksi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Delay-optimal technology mapping for in-memory computing using ReRAM devices.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A low overhead error confinement method based on application statistical characteristics.

[BibT_eX]

[DOI]

Georgios Karakonstantis

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

The Programmable Logic-in-Memory (PLiM) computer.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis.

[BibT_eX]

[DOI]

Mathias Soeken

Proceedings of the 53rd Annual Design Automation Conference, 2016

Statistical fault injection for impact-evaluation of timing errors on application performance.

[BibT_eX]

[DOI]

Georgios Karakonstantis

Proceedings of the 53rd Annual Design Automation Conference, 2016

Bypassing Parity Protected Cryptography using Laser Fault Injection in Cyber-Physical System.

[BibT_eX]

[DOI]

Proceedings of the 2nd ACM International Workshop on Cyber-Physical System Security, 2016

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

TriviA: A Fast and Secure Authenticated Encryption Scheme.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

EvoDeb: Debugging Evolving Hardware Designs.

[BibT_eX]

[DOI]

Ansuman Banerjee

Proceedings of the 28th International Conference on VLSI Design, 2015

Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture.

[BibT_eX]

[DOI]

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Trace Buffer Attack: Security versus observability study in post-silicon debug.

[BibT_eX]

[DOI]

Yuanwen Huang

Prabhat Mishra

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Design and synthesis of reconfigurable control-flow structures for CGRA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Architectural reliability estimation using design diversity.

[BibT_eX]

[DOI]

Liu Yang

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Fredkin-Enabled Transformation-Based Reversible Logic Synthesis.

[BibT_eX]

[DOI]

Mathias Soeken

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Reversible Logic Synthesis via Biconditional Binary Decision Diagrams.

[BibT_eX]

[DOI]

Alessandro Littarru

Luca Gaetano Amarù

Giovanni De Micheli

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

In-memory adder functionality in 1S1R arrays.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Direct FPGA-based power profiling for a RISC processor.

[BibT_eX]

[DOI]

Cosmin Cernazanu-Glavan

Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015

New ASIC/FPGA Cost Estimates for SHA-1 Collisions.

[BibT_eX]

[DOI]

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment.

[BibT_eX]

[DOI]

Jeremy Constantin

Lai Wang

Georgios Karakonstantis

Andreas Burg

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

Xiaolin Chen

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014

Designing stream ciphers with scalable data-widths: a case study with HC-128.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2014

Ancilla-Quantum Cost Trade-off during Reversible Logic Synthesis using Exclusive Sum-of-Products.

[BibT_eX]

[DOI]

Nilanjan Pal

Soumajit Majumder

CoRR, 2014

Complexity Analysis of Reversible Logic Synthesis.

[BibT_eX]

[DOI]

Chander Chandak

Kaushik Chakraborty

CoRR, 2014

Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR).

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Tutorial T2B: Cost / Application / Time to Market Driven SoC Design and Manufacturing Strategy.

[BibT_eX]

[DOI]

Barun Kumar De

Ansuman Banerjee

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

Alexander Fell

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Constructive Reversible Logic Synthesis for Boolean Functions with Special Properties.

[BibT_eX]

[DOI]

Proceedings of the Reversible Computation - 6th International Conference, 2014

Processor Design with Asymmetric Reliability.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Efficient Reversible Logic Synthesis via Isomorphic Subgraph Matching.

[BibT_eX]

[DOI]

Mridul Krishna

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

One Word/Cycle HC-128 Accelerator via State-Splitting Optimization.

[BibT_eX]

[DOI]

Proceedings of the Progress in Cryptology - INDOCRYPT 2014, 2014

Cryptanalysis of the Double-Feedback XOR-Chain Scheme Proposed in Indocrypt 2013.

[BibT_eX]

[DOI]

Subhadeep Banik

Anusha Chowdhury

Proceedings of the Progress in Cryptology - INDOCRYPT 2014, 2014

System-level reliability exploration framework for heterogeneous MPSoC.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Efficient Hardware Accelerator for AEGIS-128 Authenticated Encryption.

[BibT_eX]

[DOI]

Proceedings of the Information Security and Cryptology - 10th International Conference, 2014

Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013

Ingredients of Adaptability: A Survey of Reconfigurable Processors.

[BibT_eX]

[DOI]

VLSI Design, 2013

High-Performance Hardware Implementation for RC4 Stream Cipher.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Quad-RC4: Merging Four RC4 States towards a 32-bit Stream Cipher.

[BibT_eX]

[DOI]

Subhamoy Maitra

IACR Cryptol. ePrint Arch., 2013

Three Snakes in One Hole: A 67 Gbps Flexible Hardware for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2013

Optimized GPU Implementation and Performance Analysis of HC Series of Stream Ciphers.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2013

Designing integrated accelerator for stream ciphers with structural similarities.

[BibT_eX]

[DOI]

Sourav Sen Gupta

Cryptogr. Commun., 2013

Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC.

[BibT_eX]

[DOI]

Axel Acosta-Aponte

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Fast reliability exploration for embedded processors via high-level fault injection.

[BibT_eX]

[DOI]

Chao Chen

Proceedings of the International Symposium on Quality Electronic Design, 2013

Analysis and Improvement of Transformation-Based Reversible Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Opportunistic redundancy for improving reliability of embedded processors.

[BibT_eX]

[DOI]

Renlin Li

Proceedings of the 8th International Design and Test Symposium, 2013

RAPID-FeinSPN: A Rapid Prototyping Framework for Feistel and SPN-Based Block Ciphers.

[BibT_eX]

[DOI]

Proceedings of the Information Systems Security - 9th International Conference, 2013

Power modeling and estimation during ADL-driven embedded processor design.

[BibT_eX]

[DOI]

Proceedings of the 4th Annual International Conference on Energy Aware Computing Systems and Applications, 2013

SI-DFA: Sub-expression integrated Deterministic Finite Automata for Deep Packet Inspection.

[BibT_eX]

[DOI]

Rajat Sen

Proceedings of the IEEE 14th International Conference on High Performance Switching and Routing, 2013

Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

High-level modeling and synthesis for embedded FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

CoARX: a coprocessor for ARX-based cryptographic algorithms.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

New Speed Records for Salsa20 Stream Cipher Using an Autotuning Framework on GPUs.

[BibT_eX]

[DOI]

Proceedings of the Progress in Cryptology, 2013

2012

High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2012

Exploring security-performance trade-offs during hardware accelerator design of stream cipher RC4.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

ASIC synthesis using Architecture Description Language.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Design and analysis of layered coarse-grained reconfigurable architecture.

[BibT_eX]

[DOI]

Tejas Naphade

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Designing high-throughput hardware accelerator for stream cipher HC-128.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011

Combinational logic synthesis for material implication.

[BibT_eX]

[DOI]

Zoltan Endre Rakosi

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Adaptive Energy-Efficient Architecture for WCDMA Channel Estimation.

[BibT_eX]

[DOI]

Zoltan Endre Rakosi

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

HiPAcc-LTE: An Integrated High Performance Accelerator for 3GPP LTE Stream Ciphers.

[BibT_eX]

[DOI]

Sourav Sen Gupta