Anupam Chattopadhyay

According to our database1, Anupam Chattopadhyay authored at least 174 papers between 2004 and 2019.

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2019
Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures.
IET Computers & Digital Techniques, 2019

Security is an Architectural Design Constraint.
IACR Cryptology ePrint Archive, 2019

Improving Speed of Dilithium's Signing Procedure.
IACR Cryptology ePrint Archive, 2019

On Misuse of Nonce-Misuse Resistance: Adapting Differential Fault Attacks on (few) CAESAR Winners.
IACR Cryptology ePrint Archive, 2019

Mind the Portability: A Warriors Guide through Realistic Profiled Side-channel Analysis.
IACR Cryptology ePrint Archive, 2019

SoCINT: Resilient System-on-Chip via Dynamic Intrusion Detection.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

Applying Modified Householder Transform to Kalman Filter.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

Optimizing Quantum Circuits for Modular Exponentiation.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

Lightweight Secure-Boot Architecture for RISC-V System-on-Chip.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Number "Not Used" Once - Practical Fault Attack on pqm4 Implementations of NIST Candidates.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2019

2018
Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization.
IEEE Trans. Parallel Distrib. Syst., 2018

Toward Threat of Implementation Attacks on Substation Security: Case Study on Fault Detection and Isolation.
IEEE Trans. Industrial Informatics, 2018

Secure and Lightweight Compressive Sensing Using Stream Cipher.
IEEE Trans. on Circuits and Systems, 2018

Domain Wall Motion-Based Dual-Threshold Activation Unit for Low-Power Classification of Non-Linearly Separable Functions.
IEEE Trans. Biomed. Circuits and Systems, 2018

Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things.
Proceedings of the IEEE, 2018

A template-based technique for efficient Clifford+T-based quantum circuit implementation.
Microelectronics Journal, 2018

Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays.
JETC, 2018

TriviA and uTriviA: two fast and secure authenticated encryption schemes.
J. Cryptographic Engineering, 2018

Side-channel Assisted Existential Forgery Attack on Dilithium - A NIST PQC candidate.
IACR Cryptology ePrint Archive, 2018

Number "Not" Used Once - Key Recovery Fault Attacks on LWE Based Lattice Cryptographic Schemes.
IACR Cryptology ePrint Archive, 2018

On Hardware Implementation of Tang-Maitra Boolean Functions.
Proceedings of the Arithmetic of Finite Fields - 7th International Workshop, 2018

Floating Point Multiplication Mapping on ReRAM Based In-memory Computing Architecture.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Accelerating Hash Computations Through Efficient Instruction-Set Customisation.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Security Vulnerabilities of Unmanned Aerial Vehicles and Countermeasures: An Experimental Study.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

ReRAM-based In-Memory Computation of Galois Field arithmetic.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Crack me if you can: hardware acceleration bridging the gap between practical and theoretical cryptanalysis?: a Survey.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

A Blockchain Framework for Insurance Processes.
Proceedings of the 9th IFIP International Conference on New Technologies, 2018

A Security Model for Intelligent Vehicles and Smart Traffic Infrastructure.
Proceedings of the 2018 IEEE Intelligent Vehicles Symposium, 2018

BLIC: A Blockchain Protocol for Manufacturing and Supply Chain Management of ICS.
Proceedings of the IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2018

An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine Learning.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

PPAP and iPPAP: PLL-Based Protection Against Physical Attacks.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Hardware-Efficient Implementation of CLOC for On-chip Authenticated Encryption.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Synthesis, Technology Mapping and Optimization for Emerging Technologies.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Lightweight ASIC Implementation of AEGIS-128.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Synthesis of Multi-valued Literal Using Lukasiewicz Logic.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

A New High Throughput and Area Efficient SHA-3 Implementation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Efficient and Lightweight Quantized Compressive Sensing using μ-Law.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Efficient Hardware Accelerator for NORX Authenticated Encryption.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

SMARTS: secure memory assurance of RISC-V trusted SoC.
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

Domain Wall Motion-based XOR-like Activation Unit With A Programmable Threshold.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

Logic-In-Memory Architecture For Min/Max Search.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Certificate Transparency Using Blockchain.
Proceedings of the 2018 IEEE International Conference on Data Mining Workshops, 2018

DFARPA: Differential fault attack resistant physical design automation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Technology-aware logic synthesis for ReRAM based in-memory computing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

CoLPUF : A Novel Configurable LFSR-based PUF.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Secure and Tamper-resilient Distributed Ledger for Data Aggregation in Autonomous Vehicles.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

MAMI: Majority and Multi-Input Logic on Memristive Crossbar Array.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation.
IEEE Trans. VLSI Syst., 2017

RC4-AccSuite: A Hardware Acceleration Suite for RC4-Like Stream Ciphers.
IEEE Trans. VLSI Syst., 2017

Hardware Architectures for Embedded Speaker Recognition Applications: A Survey.
ACM Trans. Embedded Comput. Syst., 2017

Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design.
Parallel Processing Letters, 2017

Efficient complementary resistive switch-based crossbar array Booth multiplier.
Microelectronics Journal, 2017

Attacks in Reality: the Limits of Concurrent Error Detection Codes Against Laser Fault Injection.
J. Hardware and Systems Security, 2017

Efficient implementation of generalized Maiorana-McFarland class of cryptographic functions.
J. Cryptographic Engineering, 2017

A Comprehensive Performance Analysis of Hardware Implementations of CAESAR Candidates.
IACR Cryptology ePrint Archive, 2017

Looting the LUTs : FPGA Optimization of AES and AES-like Ciphers for Authenticated Encryption.
IACR Cryptology ePrint Archive, 2017

Threshold Implementations of GIFT: A Trade-off Analysis.
IACR Cryptology ePrint Archive, 2017

An analysis of root functions - A subclass of the Impossible Class of Faulty Functions (ICFF).
Discrete Applied Mathematics, 2017

Storages Are Not Forever.
Cognitive Computation, 2017

Efficient Binary Basic Linear Algebra Operations on ReRAM Crossbar Arrays.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Differential Fault Attack on Grain v1, ACORN v3 and Lizard.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2017

Survey of secure processors.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Automatic Test Pattern Generation for Multiple Missing Gate Faults in Reversible Circuits - Work in Progress Report.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Designing Parity Preserving Reversible Circuits.
Proceedings of the Reversible Computation - 9th International Conference, 2017

SHA-3 implementation using ReRAM based in-memory computing architecture.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Security of autonomous vehicle as a cyber-physical system.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

Looting the LUTs: FPGA Optimization of AES and AES-like Ciphers for Authenticated Encryption.
Proceedings of the Progress in Cryptology - INDOCRYPT 2017, 2017

Side-Channel Attack on STTRAM Based Cache for Cryptographic Application.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

A Practical Fault Attack on ARX-Like Ciphers with a Case Study on ChaCha20.
Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2017

Secure Cyber-Physical Systems: Current trends, tools and open research problems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

ReVAMP: ReRAM based VLIW architecture for in-memory computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A systematic security analysis of real-time cyber-physical systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Area-constrained technology mapping for in-memory computing using ReRAM devices.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
RunStream: A High-Level Rapid Prototyping Framework for Stream Ciphers.
ACM Trans. Embedded Comput. Syst., 2016

Three Snakes in One Hole: The First Systematic Hardware Accelerator Design for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes.
IEEE Trans. Computers, 2016

A Sound and Complete Axiomatization of Majority-n Logic.
IEEE Trans. Computers, 2016

RunFein: a rapid prototyping framework for Feistel and SPN-based block ciphers.
J. Cryptographic Engineering, 2016

Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Hardware Accelerator for Stream Cipher Spritz.
Proceedings of the 13th International Joint Conference on e-Business and Telecommunications (ICETE 2016), 2016

From reversible logic to quantum circuits: Logic design for an emerging technology.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Racetrack memory-based encoder/decoder for low-power interconnect architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Energy Optimization of Racetrack Memory-Based SIMON Block Cipher.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Notes on Majority Boolean Algebra.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Modified projected Landweber method for Compressive-Sensing reconstruction of images with non-orthogonal matrices.
Proceedings of the International Symposium on Integrated Circuits, 2016

Low-quantum cost circuit constructions for adder and symmetric Boolean functions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Delay-optimal technology mapping for in-memory computing using ReRAM devices.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A low overhead error confinement method based on application statistical characteristics.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

The Programmable Logic-in-Memory (PLiM) computer.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Statistical fault injection for impact-evaluation of timing errors on application performance.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Bypassing Parity Protected Cryptography using Laser Fault Injection in Cyber-Physical System.
Proceedings of the 2nd ACM International Workshop on Cyber-Physical System Security, 2016

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP.
IEEE Trans. VLSI Syst., 2015

EvoDeb: Debugging Evolving Hardware Designs.
Proceedings of the 28th International Conference on VLSI Design, 2015

Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Trace Buffer Attack: Security versus observability study in post-silicon debug.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Design and synthesis of reconfigurable control-flow structures for CGRA.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Architectural reliability estimation using design diversity.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Fredkin-Enabled Transformation-Based Reversible Logic Synthesis.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Reversible Logic Synthesis via Biconditional Binary Decision Diagrams.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

In-memory adder functionality in 1S1R arrays.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

New ASIC/FPGA Cost Estimates for SHA-1 Collisions.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

TriviA: A Fast and Secure Authenticated Encryption Scheme.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2015, 2015

Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
Designing stream ciphers with scalable data-widths: a case study with HC-128.
J. Cryptographic Engineering, 2014

Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR).
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Tutorial T2B: Cost / Application / Time to Market Driven SoC Design and Manufacturing Strategy.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Constructive Reversible Logic Synthesis for Boolean Functions with Special Properties.
Proceedings of the Reversible Computation - 6th International Conference, 2014

Processor Design with Asymmetric Reliability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Efficient Reversible Logic Synthesis via Isomorphic Subgraph Matching.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

One Word/Cycle HC-128 Accelerator via State-Splitting Optimization.
Proceedings of the Progress in Cryptology - INDOCRYPT 2014, 2014

Cryptanalysis of the Double-Feedback XOR-Chain Scheme Proposed in Indocrypt 2013.
Proceedings of the Progress in Cryptology - INDOCRYPT 2014, 2014

System-level reliability exploration framework for heterogeneous MPSoC.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Efficient Hardware Accelerator for AEGIS-128 Authenticated Encryption.
Proceedings of the Information Security and Cryptology - 10th International Conference, 2014

Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Ingredients of Adaptability: A Survey of Reconfigurable Processors.
VLSI Design, 2013

High-Performance Hardware Implementation for RC4 Stream Cipher.
IEEE Trans. Computers, 2013

Quad-RC4: Merging Four RC4 States towards a 32-bit Stream Cipher.
IACR Cryptology ePrint Archive, 2013

Three Snakes in One Hole: A 67 Gbps Flexible Hardware for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes.
IACR Cryptology ePrint Archive, 2013

Designing integrated accelerator for stream ciphers with structural similarities.
Cryptography and Communications, 2013

Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Fast reliability exploration for embedded processors via high-level fault injection.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Analysis and Improvement of Transformation-Based Reversible Logic Synthesis.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Opportunistic redundancy for improving reliability of embedded processors.
Proceedings of the 8th International Design and Test Symposium, 2013

RAPID-FeinSPN: A Rapid Prototyping Framework for Feistel and SPN-Based Block Ciphers.
Proceedings of the Information Systems Security - 9th International Conference, 2013

Power modeling and estimation during ADL-driven embedded processor design.
Proceedings of the 4th Annual International Conference on Energy Aware Computing Systems and Applications, 2013

SI-DFA: Sub-expression integrated Deterministic Finite Automata for Deep Packet Inspection.
Proceedings of the IEEE 14th International Conference on High Performance Switching and Routing, 2013

Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design.
Proceedings of the Design, Automation and Test in Europe, 2013

High-level modeling and synthesis for embedded FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2013

CoARX: a coprocessor for ARX-based cryptographic algorithms.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

New Speed Records for Salsa20 Stream Cipher Using an Autotuning Framework on GPUs.
Proceedings of the Progress in Cryptology, 2013

2012
High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures.
Int. J. Reconfig. Comp., 2012

Designing Integrated Accelerator for Stream Ciphers with Structural Similarities.
IACR Cryptology ePrint Archive, 2012

Exploring security-performance trade-offs during hardware accelerator design of stream cipher RC4.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

ASIC synthesis using Architecture Description Language.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Design and analysis of layered coarse-grained reconfigurable architecture.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Designing high-throughput hardware accelerator for stream cipher HC-128.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Optimized GPU Implementation and Performance Analysis of HC Series of Stream Ciphers.
Proceedings of the Information Security and Cryptology - ICISC 2012, 2012

FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
Combinational logic synthesis for material implication.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Adaptive Energy-Efficient Architecture for WCDMA Channel Estimation.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

HiPAcc-LTE: An Integrated High Performance Accelerator for 3GPP LTE Stream Ciphers.
Proceedings of the Progress in Cryptology - INDOCRYPT 2011, 2011

2010
Automatic Generation of Memory Interfaces for ASIPs.
IJERTCS, 2010

2008
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.
IEEE Trans. VLSI Syst., 2008

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.
ACM Trans. Embedded Comput. Syst., 2008

Power-efficient Instruction Encoding Optimization for Various Architecture Classes.
JCP, 2008

High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Power-efficient Instruction Encoding Optimization for Embedded Processors.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Increasing data-bandwidth to instruction-set extensions through register clustering.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Design space exploration of partially re-configurable embedded processors.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Integrated Verification Approach during ADL-Driven Processor Design.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

Automatic ADL-based operand isolation for embedded processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Optimization Techniques for ADL-Driven RTL Processor Synthesis.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
RTL Processor Synthesis for Architecture Exploration and Implementation.
Proceedings of the 2004 Design, 2004


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