Bahniman Ghosh

According to our database1, Bahniman Ghosh authored at least 23 papers between 2013 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
Innovative design methodologies in quantum-dot cellular automata.
Int. J. Circuit Theory Appl., 2015

2014
<i>Ab-Initio</i> Modeling of Effect of Boron and Phosphorus Doping in CoFe/MgO Magnetic Tunnel Junctions.
J. Low Power Electron., 2014

Read and Write Analysis for Balanced Pattern Memristor Crossbar Array.
J. Low Power Electron., 2014

Domain Wall Dynamics Due to Voltage Controlled Magnetic Anisotropy.
J. Low Power Electron., 2014

In<sub>0</sub> <sub>25</sub>Ga<sub>0</sub> <sub>75</sub>As Channel Double Gate Junctionless Transistor.
J. Low Power Electron., 2014

Impact of High- Spacer on Junctionless Transistor in Sub-Threshold Regime.
J. Low Power Electron., 2014

Quantum-Dot Cellular Automata-Implementing Reversible Benchmarks.
J. Low Power Electron., 2014

Effect of Nanoribbon Width and Strain on the Electronic Properties of the WS2 Nanoribbon.
J. Low Power Electron., 2014

Spin Transport in Single Layer Germanene: The Role of Electron Electron Scattering.
J. Low Power Electron., 2014

Device Physics of Germanium-Junctionless Tunnel Field Effect Transistor and an Approach to Optimize <i>I</i> <sub>on</sub>/<i>I</i> <sub>off</sub> by Drain Engineering and Work Function Engineering.
J. Low Power Electron., 2014

Performance Improvement in Nanoscale Ge-GaAs Heterojunction Junctionless Tunnel FET Using a Dual Material Gate.
J. Low Power Electron., 2014

2-Bit Full Adder Implementation Using Single Spin Logic Paradigm.
J. Low Power Electron., 2014

Clocking Scheme Implementation for Multi-Layered Quantum Dot Cellular Automata Design.
J. Low Power Electron., 2014

Simulation of 2 Bit by 2 Bit Binary Multiplier Using Magnetic Tunnel Junction Device.
J. Low Power Electron., 2014

Effect of Traps on the Performance of Nanowire Si Junctionless Tunnel FET.
J. Low Power Electron., 2014

Junctionless Silicon-Nanowire Gate-All-Around Tunnel Field Effect Transistor.
J. Low Power Electron., 2014

Design of a Multi-Layered QCA Configurable Logic Block for FPGAs.
J. Circuits Syst. Comput., 2014

Transistor size optimization in digital circuits using ant colony optimization for continuous domain.
Int. J. Circuit Theory Appl., 2014

Performance Analysis of Spin Transfer Torque Random Access Memory with cross shaped free layer using Heusler Alloys by using micromagnetic studies.
CoRR, 2014

2013
Effect of Self Heating on Selective Buried Oxide and Silicon on Insulator Based Junctionless Transistors.
J. Low Power Electron., 2013

Junctionless Tunnel Field Effect Transistor with Enhanced Performance Using III-V Semiconductor.
J. Low Power Electron., 2013

A Novel Approach of Full Adder and Arithmetic Logic Unit Design in Quantum Dot Cellular Automata.
J. Low Power Electron., 2013

Ultrathin Compound Semiconductor in Bulk Planar Junctionless Transistor for High-Performance Nanoscale Transistors.
J. Low Power Electron., 2013


  Loading...