Neelam Surana

Orcid: 0000-0002-7841-8541

According to our database1, Neelam Surana authored at least 11 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy.
ACM Trans. Archit. Code Optim., June, 2023

2022
A 10T, 0.22fJ/Bit/Search Mixed-V<sub>T</sub> Pseudo Precharge-Free Content Addressable Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural Networks.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

2021
HyGain: High Performance, Energy-Efficient Hybrid Gain Cell based Cache Hierarchy.
CoRR, 2021

2020
A Mathematical Approach Towards Quantization of Floating Point Weights in Low Power Neural Networks.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

A Low-Voltage Split Memory Architecture for Binary Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Robust and High-Performance 12-T Interlocked SRAM for In-Memory Computing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Energy Efficient Single-Ended 6-T SRAM for Multimedia Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder.
IET Comput. Digit. Tech., 2019

Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia Applications.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2014
In<sub>0</sub> <sub>25</sub>Ga<sub>0</sub> <sub>75</sub>As Channel Double Gate Junctionless Transistor.
J. Low Power Electron., 2014


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