Benjamin Stefan Devlin

According to our database, Benjamin Stefan Devlin authored at least 11 papers between 2009 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments.

Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada

IEICE Trans. Electron., 2013

2012

Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling.

Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada

IEICE Trans. Electron., 2012

Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation.

Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada

Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012

Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes.

Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada

Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011

A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation.

Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada

IEEE J. Solid State Circuits, 2011

Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA.

Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system.

Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS.

Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment.

Benjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging.

Kunihiro Asada, Makoto Ikeda, Benjamin Stefan Devlin, Taku Sogabe

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA.

Benjamin Stefan Devlin, MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada

Proceedings of the 35th European Solid-State Circuits Conference, 2009