Toru Nakura

According to our database1, Toru Nakura authored at least 82 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field.
IEEE Trans. Instrum. Meas., 2019

A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool.
IEICE Electron. Express, 2019

Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes.
IEICE Electron. Express, 2019

2018
Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting.
IEICE Trans. Electron., 2018

Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction.
IEICE Trans. Electron., 2018

Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Time-domain approach for analog circuits in deep sub-micron LSI.
IEICE Electron. Express, 2018

Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment.
J. Electron. Test., 2018

A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

2017
A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring.
IEICE Trans. Electron., 2017

A PLL Compiler from Specification to GDSII.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Impulse signal generator based on current-mode excitation and transmission line resonator.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Extension of power supply impedance emulation method on ATE for multiple power domain.
Proceedings of the 22nd IEEE European Test Symposium, 2017

High Spatial Resolution Detection Method for Point Light Source in Scintillator.
Proceedings of the Computational Imaging XV, Burlingame, 2017

A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

CMOS-on-quartz pulse generator for low power applications.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors.
J. Circuits Syst. Comput., 2016

An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface.
IEICE Trans. Electron., 2016

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing.
IEICE Trans. Electron., 2016

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing.
J. Electron. Test., 2016

Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board.
Proceedings of the 2016 IEEE International Test Conference, 2016

Fully automated PLL compiler generating final GDS from specification.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Resonant power supply noise reduction using a triangular active charge injection.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise.
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Analytical design optimization of sub-ranging ADC based on stochastic comparator.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer.
IEICE Trans. Electron., 2015

Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline.
IEICE Electron. Express, 2015

Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator.
Proceedings of the Nordic Circuits and Systems Conference, 2015

An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

A Technique for Analyzing On-Chip Power Supply Impedance.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

A calibration-free time difference accumulator using two pulses propagating on a single buffer ring.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills.
Proceedings of the 2014 International Test Conference, 2014

Streaming distribution of a live seminar: Rudimentary knowledge for LSI design.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Burst-pulse Generator based on transmission line toward sub-MMW.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems.
IEICE Trans. Electron., 2013

Low pass filter-less pulse width controlled PLL with zero phase offset using pulse width accumulator.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

A Pulse Width controlled PLL and its automated design flow.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter.
IEICE Trans. Electron., 2012

Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme.
IEICE Trans. Electron., 2012

On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction.
IEICE Trans. Electron., 2012

Power integrity control of ATE for emulating power supply fluctuations on customer environment.
Proceedings of the 2012 IEEE International Test Conference, 2012

7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Impact of All-Digital PLL on SoC Testing.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Cascaded Time Difference Amplifier with Differential Logic Delay Cell.
IEICE Trans. Electron., 2011

1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells.
IEICE Trans. Electron., 2011

On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch.
IEICE Trans. Electron., 2011

All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter.
IEICE Trans. Electron., 2011

Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy.
Proceedings of the International SoC Design Conference, 2011

On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

Decoupling capacitance boosting for on-chip resonant supply noise reduction.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Time Difference Amplifier with Robust Gain Using Closed-Loop Control.
IEICE Trans. Electron., 2010

A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A 8bit two stage time-to-digital converter using time difference amplifier.
IEICE Electron. Express, 2010

Time-to-digital converter based on time difference amplifier with non-linearity calibration.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Cascaded time difference amplifier using differential logic delay cell.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability.
IEICE Trans. Electron., 2009

Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Measurement of power supply noise tolerance of self-timed processor.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2007
Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

LAGS System Using Data/Instruction Grain Power Control.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Design of Active Substrate Noise Canceller using Power Supply di/dt Detector.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Autonomous <i>di/dt</i> Control of Power Supply for Margin Aware Operation.
IEICE Trans. Electron., 2006

Feedforward Active Substrate Noise Cancelling Based on <i>di/dt</i> of Power Supply.
IEICE Trans. Electron., 2006

2005
Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs.
IEICE Trans. Electron., 2005

On-chip <i>di/dt</i> Detector Circuit.
IEICE Trans. Electron., 2005

Stub vs. Capacitor for Power Supply Noise Reduction.
IEICE Trans. Electron., 2005


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