Bharat Choudhary

According to our database, Bharat Choudhary authored at least 8 papers between 2016 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A Low-Phase Noise, Low-Power PFD Circuit Using GDI and Pass Transistor Logic with PVT tolerance.

Dheeraj Singh Rajput, Bharat Choudhary, Archana Singhal, Dharmendar Boolchandani

Proceedings of the IEEE International Conference on Consumer Electronics, 2026

2025

NQS Small-Signal Circuit Modelling of GaN-SOI-FinFET for RF/Wireless Applications.

Vandana Singh Rajawat, Bharat Choudhary, Ajay Kumar

Circuits Syst. Signal Process., August, 2025

2024

Performance Assessment of High-k SOI GaN FinFET with Different Fin Aspect Ratio for RF/Wireless Applications.

Vandana Singh Rajawat, Bharat Choudhary, Ajay Kumar

Wirel. Pers. Commun., May, 2024

Assessing Model Fusion Efficacy Through Hierarchical Knowledge Distillation.

Bharat Choudhary, Deepak Singh, Dilip Singh Sisodia

Proceedings of the Machine Learning, Image Processing, Network Security and Data Sciences, 2024

2018

MCML Dynamic Register Design.

Neeta Pandey, Kirti Gupta, Bharat Choudhary

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies.

Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal

J. Circuits Syst. Comput., 2017

2016

New Proposal for MCML Based Three-Input Logic Implementation.

Neeta Pandey, Kirti Gupta, Bharat Choudhary

VLSI Design, 2016

MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells.

Neeta Pandey, Kirti Gupta, Garima Bhatia, Bharat Choudhary

Microelectron. J., 2016