Dharmendar Boolchandani

Orcid: 0000-0001-8793-3484

According to our database1, Dharmendar Boolchandani authored at least 15 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2024
Programmable Readout With Integrated Bandgap Reference Potentiostat for Glucose Sensing.
IEEE Trans. Instrum. Meas., 2024

2023
A Novel Wide Tuning Range Differential Ring Oscillator Application in Dynamically Stable and 1.17 $\upmu $s Lock Time CP-PLL Frequency Synthesizer.
Circuits Syst. Signal Process., December, 2023

Optimization of Performance Parameters of Phase Frequency Detector Using Taguchi DoE and Pareto ANOVA Techniques.
J. Circuits Syst. Comput., June, 2023

Novel tunable current feedback instrumentation amplifier based on BBFC OP-AMP for biomedical applications with low power and high CMRR.
Integr., May, 2023

Novel Programmable Readout Amplifier and Potentiostat for Glucose Sensing Applications.
SN Comput. Sci., March, 2023

Programmable Transimpedance Amplifier with Integrated Bandgap Reference for Glucose Concentration Measurement.
CoRR, 2023

A Signal Conditioning Circuit with Integrated Bandgap Reference for Glucose Concentration Measurement.
Proceedings of the Internet of Things. Advances in Information and Communication Technology, 2023

2022
A High Speed Phase Detection Circuit with No Dead Zone Suitable for Minimal Jitter and Low Power Applications.
J. Circuits Syst. Comput., 2022

Low Power, Wide Range Synthesizer for 534 MHz-18.56 GHz Band with FoM of - 192.45 dBc/Hz.
J. Circuits Syst. Comput., 2022

A novel instrumentation amplifier with high tunable gain and CMRR forbiomedical applications.
Turkish J. Electr. Eng. Comput. Sci., 2022

2021
A brief review of the various phase-frequency detector architectures.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Design of potentiostat and current mode read-out amplifier for glucose sensing.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2016
Variability and reliability aware surrogate model for sensing delay analysis of SRAM sense amplifier.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015
Optimal Tuning of PID Controller for Centrifugal Temperature Control System in Sugar Industry Using Genetic Algorithm.
Proceedings of Fifth International Conference on Soft Computing for Problem Solving, 2015

2013
Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013


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