Biao Min

Orcid: 0000-0002-9296-4063

According to our database1, Biao Min authored at least 12 papers between 2013 and 2019.

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Bibliography

2019
A robust background initialization algorithm with superpixel motion detection.
Signal Process. Image Commun., 2019

A high performance hardware architecture for non-negative tensor factorization.
Microelectron. J., 2019

High performance hardware architecture for singular spectrum analysis of Hankel tensors.
Microprocess. Microsystems, 2019

A Data-Center FPGA Acceleration Platform for Convolutional Neural Networks.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018
A fast inter CU decision algorithm for HEVC.
Signal Process. Image Commun., 2018

2017
A Fully Pipelined Hardware Architecture for Intra Prediction of HEVC.
IEEE Trans. Circuits Syst. Video Technol., 2017

Fast HEVC intra coding decision based on statistical cost and corner detection.
Proceedings of the International Conference on Systems, Signals and Image Processing, 2017

2015
A Fast CU Size Decision Algorithm for the HEVC Intra Encoder.
IEEE Trans. Circuits Syst. Video Technol., 2015

2013
A Flexible and Customizable Architecture for the Relaxation Labeling Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Parallel architecture for DNA sequence inexact matching with Burrows-Wheeler Transform.
Microelectron. J., 2013

Noise filtering and occurrence identification of mouse ultrasonic vocalization call.
Proceedings of the International Conference on Machine Learning and Cybernetics, 2013

A customizable Stochastic State Point Process Filter (SSPPF) for neural spiking activity.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013


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