Yao Xin

According to our database, Yao Xin authored at least 22 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Recursive Multi-Tree Construction With Efficient Rule Sifting for Packet Classification on FPGA.

Yao Xin, Wenjun Li, Chengjun Jia, Xianfeng Li, Yang Xu, Bin Liu, Zhihong Tian, Weizhe Zhang

IEEE/ACM Trans. Netw., April, 2024

2023

A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets.

Yao Xin, Wenjun Li, Gaogang Xie, Yang Xu, Yi Wang

IEEE Micro, 2023

MCCQF: Low-Latency Transmission Based on IEEE 802.1 Qch For Hierarchical Networking.

Yan Liu, Dajun Zhou, Shuangping Zhan, Yao Xin, Jiashuo Lin, Xingbo Feng, Enze Shi, Ye Qi, Gang Chen, Junqing Zheng, Yi Wang, Xiao Zheng

Proceedings of the IEEE International Conference on Communications, 2023

Building a High-Performance Data Channel for the Federal Cyber Range.

Zengxie Ma, Ning Hu, Bo Qu, Yao Xin, Shengan Song, Xinyi Qiu

Proceedings of the 8th International Conference on Data Science in Cyberspace, 2023

Comparative analysis of neural networks techniques to forecast Airfare Prices.

Alessandro Aliberti, Yao Xin, Alessio Viticchié, Enrico Macii, Edoardo Patti

Proceedings of the 47th IEEE Annual Computers, Software, and Applications Conference, 2023

2022

FPGA-Based Updatable Packet Classification Using TSS-Combined Bit-Selecting Tree.

Yao Xin, Wenjun Li, Guoming Tang, Tong Yang, Xiaohe Hu, Yi Wang

IEEE/ACM Trans. Netw., 2022

High Throughput Hardware/Software Heterogeneous System for RRPN-Based Scene Text Detection.

Yao Xin, Donald Donglong Chen, Chongyang Zeng, Weichen Zhang, Yi Wang, Ray C. C. Cheung

IEEE Trans. Computers, 2022

A Versatility-Performance Balanced Hardware Architecture for Scene Text Detection.

Yao Xin, Guoming Tang, Donglong Chen, Rumin Zhang, Teng Liang, Ray C. C. Cheung, Çetin Kaya Koç

Proceedings of the IEEE Smartworld, 2022

Updatable Packet Classification on FPGA with Bounded Worst-Case Performance.

Yao Xin, Wenjun Li, Gaogang Xie, Yang Xu, Yi Wang

Proceedings of the IEEE Symposium on High-Performance Interconnects, 2022

HybridTSS: A Recursive Scheme Combining Coarse- and Fine- Grained Tuples for Packet Classification.

Yuxi Liu, Yao Xin, Wenjun Li, Haoyu Song, Ori Rottenstreich, Gaogang Xie, Weichao Li, Yi Wang

Proceedings of the 6th Asia-Pacific Workshop on Networking, 2022

2021

An FPGA-based High-Throughput Packet Classification Architecture Supporting Dynamic Updates for Large-Scale Rule Sets.

Yao Xin, Wenjun Li, Yi Wang, Song Yao

Proceedings of the 2021 IEEE Conference on Computer Communications Workshops, 2021

KickTree: A Recursive Algorithmic Scheme for Packet Classification with Bounded Worst-Case Performance.

Yao Xin, Yuxi Liu, Wenjun Li, Ruyi Yao, Yang Xu, Yi Wang

Proceedings of the ANCS '21: Symposium on Architectures for Networking and Communications Systems, Layfette, IN, USA, December 13, 2021

2016

An FPGA-Based High-Performance Neural Ensemble Spiking Activity Simulator Utilizing Generalized Volterra Kernel and Complexity Analysis.

Will X. Y. Li, Ray C. C. Cheung, Yao Xin, Dong Song, Theodore W. Berger

J. Circuits Syst. Comput., 2016

FPGA-Based High-Performance Collision Detection: An Enabling Technique for Image-Guided Robotic Surgery.

Zhaorui Zhang, Yao Xin, Benben Liu, Will X. Y. Li, Kit-Hang Lee, Chun-Fai Ng, Danail Stoyanov, Ray C. C. Cheung, Ka-Wai Kwok

Frontiers Robotics AI, 2016

2015

An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics.

Yao Xin, Will X. Y. Li, Zhaorui Zhang, Ray C. C. Cheung, Dong Song, Theodore W. Berger

IEEE ACM Trans. Comput. Biol. Bioinform., 2015

2014

An FPGA based scalable architecture of a stochastic state point process filter (SSPPF) to track the nonlinear dynamics underlying neural spiking.

Yao Xin, Will X. Y. Li, Ray C. C. Cheung, Rosa H. M. Chan, Hong Yan, Dong Song, Theodore W. Berger

Microelectron. J., 2014

GPU-based biclustering for microarray data analysis in neurocomputing.

Benben Liu, Yao Xin, Ray C. C. Cheung, Hong Yan

Neurocomputing, 2014

VLSI architecture of a high-performance neural spiking activity simulator based on generalized Volterra kernel.

Will X. Y. Li, Yao Xin, Dong Song, Theodore W. Berger, Ray C. C. Cheung

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Laguerre-volterra model and architecture for MIMO system identification and output prediction.

Will X. Y. Li, Yao Xin, Rosa H. M. Chan, Dong Song, Theodore W. Berger, Ray C. C. Cheung

Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

2013

Parallel architecture for DNA sequence inexact matching with Burrows-Wheeler Transform.

Yao Xin, Benben Liu, Biao Min, Will X. Y. Li, Ray C. C. Cheung, Anthony S. Fong, Ting-Fung Chan

Microelectron. J., 2013

Erratum to "Finding the most efficient DMUs in DEA: An improved integrated model" [Comput. Indus. Eng. 52 (2007) 71-77].

Yan Q. You, Tao Jie, Yao Xin

Comput. Ind. Eng., 2013

A customizable Stochastic State Point Process Filter (SSPPF) for neural spiking activity.

Yao Xin, Will X. Y. Li, Biao Min, Yan Han, Ray C. C. Cheung

Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013