Bosco H. Leung

Orcid: 0000-0003-4509-172X

Affiliations:
  • University of Waterloo, Canada


According to our database1, Bosco H. Leung authored at least 23 papers between 1992 and 2016.

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Bibliography

2016
Noise Spike Model in Relaxation Oscillators Based on Physical Phase Change.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Design Techniques for Linearity in Time-Based ΣΔ Analog-to-Digital Converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

2014
Truly Random Number Generator Based on a Ring Oscillator Utilizing Last Passage Time.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Novel dissipative Lagrange-Hamilton formalism for LC/van der pol oscillator with new implication on phase noise dependency on quality factor.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013
Design and Analysis of Saturated Ring Oscillators Based on the Random Mid-Point Voltage Concept.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2012
Noise/jump phenomenon of relaxation oscillators based on phase change using path integral/lagrangian formulation in quantum mechanics.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2010
A Switching-Based Phase Noise Model for CMOS Ring Oscillators Based on Multiple Thresholds Crossing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Dynamic Quadrant Swapping Scheme Implemented in a Post Conversion Block for I, Q Mismatch Reduction in a DQPSK Receiver.
IEEE J. Solid State Circuits, 2010

2009
Phase Noise of a Class of Ring Oscillators Having Unsaturated Outputs With Focus on Cycle-to-Cycle Correlation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2004
Investigation of phase noise of ring oscillators with time-varying current and noise sources by time-scaling thermal noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A novel model on phase noise of ring oscillator based on last passage time.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture.
IEEE J. Solid State Circuits, 2004

1999
A 400-MHz, 12-bit, 18-mW, IF digitizer with mixer inside a sigma-delta modulator loop.
IEEE J. Solid State Circuits, 1999

1998
A 150 MHz 13b 12.5 mW IF digitizer.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997
A 0.25-mW low-pass passive sigma-delta modulator with built-in mixer for a 10-MHz IF input.
IEEE J. Solid State Circuits, 1997

A 1.95-V, 0.34-mW, 12-b sigma-delta modulator stabilized by local feedback loops.
IEEE J. Solid State Circuits, 1997

1996
A class-AB high-speed low-power operational amplifier in BiCMOS technology.
IEEE J. Solid State Circuits, 1996

1995
BiCMOS circuits for high speed current mode D/A converters.
IEEE J. Solid State Circuits, August, 1995

A high resolution multibit sigma-delta modulator with individual level averaging.
IEEE J. Solid State Circuits, April, 1995

1994
A Mismatch Independent DNL Pipelined Analog to Digital Converter.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Quantization Noise of 1-Bit Double-Loop Sigma-Delta Modulator.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
A Low-power Class-AB BiCMOS Opamp Using "Pseudo-pnp" Transistors.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992
STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992


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