Bouraoui Ouni

Orcid: 0000-0001-5708-3802

According to our database1, Bouraoui Ouni authored at least 36 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
DTR-HAR: deep temporal residual representation for human activity recognition.
Vis. Comput., 2022

2021
Two hardware implementations for modular multiplication in the AMNS: Sequential and semi-parallel.
J. Inf. Secur. Appl., 2021

LAHAR-CNN: human activity recognition from one image using convolutional neural network learning approach.
Int. J. Biom., 2021

2020
CNN-SVM Learning Approach Based Human Activity Recognition.
Proceedings of the Image and Signal Processing - 9th International Conference, 2020

2019
An Ultra-Low Power Parity Generator Circuit Based on QCA Technology.
J. Electr. Comput. Eng., 2019

An Efficient Design of DCT Approximation Based on Quantum Dot Cellular Automata (QCA) Technology.
J. Electr. Comput. Eng., 2019

High-level optimised systems design using hardware-software partitioning.
Int. J. Adv. Intell. Paradigms, 2019

Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis.
IET Circuits Devices Syst., 2019

Efficient GPU Implementation of Lucas-Kanade through OpenACC.
Proceedings of the 14th International Joint Conference on Computer Vision, 2019

Memory Efficient Deployment of an Optical Flow Algorithm on GPU Using OpenMP.
Proceedings of the Image Analysis and Processing - ICIAP 2019, 2019

Hardware Optimization on FPGA for the Modular Multiplication in the AMNS Representation.
Proceedings of the Risks and Security of Internet and Systems, 2019

2018
Single-channel-based automatic drowsiness detection architecture with a reduced number of EEG features.
Microprocess. Microsystems, 2018

Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction.
Int. J. Reconfigurable Comput., 2018

Parallel video processing on FPGA architecture.
Int. J. High Perform. Syst. Archit., 2018

Efficient design of BinDCT in quantum-dot cellular automata (QCA) technology.
IET Image Process., 2018

Harris corner detection on a NUMA manycore.
Future Gener. Comput. Syst., 2018

Evaluation of an OPENMP Parallelization of Lucas-Kanade on a NUMA-Manycore.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

Design of Efficient Quantum-Dot Cellular Automata (QCA) MAC Unit.
Proceedings of the 30th International Conference on Microelectronics, 2018

2017
Design of hardware RGB to HMMD converter based on reversible logic.
IET Image Process., 2017

A metaheuristic based on the tabu search for hardware-software partitioning.
Turkish J. Electr. Eng. Comput. Sci., 2017

2016
Online Adaptive Filters to Classify Left and Right Hand Motor Imagery.
Proceedings of the 9th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2016), 2016

Real-time image and video processing: Method and architecture.
Proceedings of the 2nd International Conference on Advanced Technologies for Signal and Image Processing, 2016

Software application for simulation-based AES, RSA and elliptic-curve algorithms.
Proceedings of the 2nd International Conference on Advanced Technologies for Signal and Image Processing, 2016

A comparison between ANN and SVM classifier for drowsiness detection based on single EEG channel.
Proceedings of the 2nd International Conference on Advanced Technologies for Signal and Image Processing, 2016

Detecting driver drowsiness based on single electroencephalography channel.
Proceedings of the 13th International Multi-Conference on Systems, Signals & Devices, 2016

2015
Hardware software partitioning of control data flow graph on system on programmable chip.
Microprocess. Microsystems, 2015

Modules placement technique under constraint of FPGA forbidden zones.
Int. J. Comput. Sci. Eng., 2015

2014
Temporal partitioning of data flow graphs for reconfigurable architectures.
Int. J. Comput. Sci. Eng., 2014

Integrated temporal partitioning and partial reconfiguration techniques for design latency improvement.
Evol. Syst., 2014

2013
Online Scheduling and Placement of Hardware Modules on Partially Dynamic Architectures.
J. Circuits Syst. Comput., 2013

2012
A partitioning methodology that optimizes the communication cost for reconfigurable computing systems.
Int. J. Autom. Comput., 2012

2011
Temporal partitioning of data flow graph for dynamically reconfigurable architecture.
J. Syst. Archit., 2011

Partitioning and scheduling technique for run time reconfigured systems.
Int. J. Comput. Aided Eng. Technol., 2011

Combining temporal partitioning and temporal placement techniques for communication cost improvement.
Adv. Eng. Softw., 2011

2007
An efficient list scheduling algorithm for time placement problem.
Comput. Electr. Eng., 2007

2004
Synthesis and Time Partitioning for Reconfigurable Systems.
Des. Autom. Embed. Syst., 2004


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