Ridha Djemal

According to our database1, Ridha Djemal authored at least 13 papers between 1996 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Single-channel-based automatic drowsiness detection architecture with a reduced number of EEG features.
Microprocessors and Microsystems - Embedded Hardware Design, 2018

2017
A Hardware/Software Prototype of EEG-based BCI System for Home Device Control.
Signal Processing Systems, 2017

2016
Online Adaptive Filters to Classify Left and Right Hand Motor Imagery.
Proceedings of the 9th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2016), 2016

A DWT-entropy-ANN based architecture for epilepsy diagnosis using EEG signals.
Proceedings of the 2nd International Conference on Advanced Technologies for Signal and Image Processing, 2016

2013
An Embedded System Architecture of Automatic censored Ordered Statistic Detector Techniques.
Journal of Circuits, Systems, and Computers, 2013

An adaptive CFAR embedded system architecture for target detection.
Design Autom. for Emb. Sys., 2013

Design of priority-based active queue management for a high-performance IP switch.
Computers & Electrical Engineering, 2013

2009
Efficient hardware architecture of 2D-scan-based wavelet watermarking for image and video.
Computer Standards & Interfaces, 2009

2005
A novel formal verification approach for RTL hardware IP cores.
Computer Standards & Interfaces, 2005

2004
High performance architecture of integrated protocols for encoded video application.
Computer Standards & Interfaces, 2004

2001
A Flow Control Approach for Encoded Video Applications Over ATM Network.
Proceedings of the Sixth IEEE Symposium on Computers and Communications (ISCC 2001), 2001

2000
Rapid prototyping of an ATM programmable associative operator.
Journal of Systems Architecture, 2000

1996
Toward reconfigurable associative architecture for high speed communication operators.
Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), 1996


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