Brajesh Pandey

According to our database, Brajesh Pandey authored at least 7 papers between 2007 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection.

Binod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Revisiting random access scan for effective enhancement of post-silicon observability.

Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, Brajesh Pandey, Virendra Singh

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016

Skip-scan: A methodology for test time reduction.

Binod Kumar, Boda Nehru, Brajesh Pandey, Jaynarayan T. Tudu

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture.

Binod Kumar, Boda Nehru, Brajesh Pandey, Virendra Singh, Jaynarayan T. Tudu

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2013

A Novel Approach for On-chip Step Down DC-to-DC Converter with DC Voltage Control.

Brajesh Pandey

Proceedings of the Asia Modelling Symposium 2013, 2013

Modeling, Simulation of Multi Standard Wireless Receivers in MATLAB/SIMULINK.

Brajesh Pandey

Proceedings of the Asia Modelling Symposium 2013, 2013

2007

Precision Low Voltage and Current References.

Brajesh Pandey, Arun N. Chandorkar

J. Low Power Electron., 2007