Virendra Singh

Mahendra Pratap Singh

Saumya Hegde

Maanak Gupta

IEEE Access, 2024

MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA Architectures.

[BibT_eX]

[DOI]

Chandramani Chaudhary

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Early Execution for Soft Error Detection.

[BibT_eX]

[DOI]

Raj Kumar Choudhary

Janeel Patel

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

GNNDLD: Graph Neural Network with Directional Label Distribution.

[BibT_eX]

[DOI]

Chandramani Chaudhary

N. Sangeeth

Proceedings of the 16th International Conference on Agents and Artificial Intelligence, 2024

2023

TSPD: A Robust Online Time Series Two-Stage Peak Detection Algorithm.

[BibT_eX]

[DOI]

Aditi Gupta

Adeiza James Onumanyi

Yamuna Prasad

Proceedings of the IEEE International Conference on Service-Oriented System Engineering, 2023

SSSN: Secured Streaming Scan Network.

[BibT_eX]

[DOI]

Sonali Shukla

Bhavika Ranjeet Kumar

B. K. S. V. L. Varaprasad

Proceedings of the 24th IEEE Latin American Test Symposium, 2023

LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Latin American Test Symposium, 2023

Optimization of Imprecise Multiplier Circuits by using Binary Decision Diagram.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture.

[BibT_eX]

[DOI]

Raghunandana K. K

Matteo Sonza Reorda

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

On-Chip SRAM Disclosure Attack Prevention Technique for SoC.

[BibT_eX]

[DOI]

Prokash Ghosh

Yogesh Gholap

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

ERrOR: Improving Performance and Fault Tolerance Using Early Execution.

[BibT_eX]

[DOI]

Raj Kumar Choudhary

Janeel Patel

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

Secure KNN Computation on Cloud.

[BibT_eX]

[DOI]

Tikaram Sanyashi

Proceedings of the Information Systems Security - 19th International Conference, 2023

DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

On Attacking Scan-based Logic Locking Schemes.

[BibT_eX]

[DOI]

Govind Rajhans Jadhav

Sonali Shukla

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

SMASh: A State Encoding Methodology Against Attacks on Finite State Machines.

[BibT_eX]

[DOI]

Gowthami Konganapalle

Sonali Shukla

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022

Approximating Arithmetic Circuits for IoT Devices Data Processing.

[BibT_eX]

[DOI]

Comput. Ind. Eng., 2022

Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction Cache.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

PASS-P: Performance and Security Sensitive Dynamic Cache Partitioning.

[BibT_eX]

[DOI]

Pranil Joshi

B. K. S. V. L. Varaprasad

Proceedings of the 19th International Conference on Security and Cryptography, 2022

REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture.

[BibT_eX]

[DOI]

Raghunandana K. K

Matteo Sonza Reorda

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021

Enhanced Design Debugging With Assistance From Guidance-Based Model Checking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A Framework for Configurable Joint-Scan Design-for-Test Architecture.

[BibT_eX]

[DOI]

J. Electron. Test., 2021

Locality-based Graph Reordering for Processing Speed-Ups and Impact of Diameter.

[BibT_eX]

[DOI]

Vedant Satav

CoRR, 2021

DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2021

Fine-Grained Scheduling in Heterogeneous-ISA Architectures.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2021

Enhancing Testbench Quality via Genetic Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Dynamic Optimizations in GPU Using Roofline Model.

[BibT_eX]

[DOI]

Winnie Thomas

Suryakant Toraskar

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Predictive Warp Scheduling for Efficient Execution in GPGPU.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Secrecy Rate Maximization at Near User in Untrusted NOMA with Trusted DF Relay.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2021

2020

A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

PIM-GraphSCC: PIM-Based Graph Processing Using Graph's Community Structures.

[BibT_eX]

[DOI]

Newton

Trevor E. Carlson

IEEE Comput. Archit. Lett., 2020

A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Characterization of Data Generating Neural Network Applications on x86 CPU Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

LUT-based Circuit Approximation with Targeted Error Guarantees.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

Soft-error reliable architecture for future microprocessors.

[BibT_eX]

[DOI]

Shoba Gopalakrishnan

IET Comput. Digit. Tech., 2019

SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement.

[BibT_eX]

[DOI]

J. Electron. Test., 2019

On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Towards Energy Efficient non-von Neumann Architectures for Deep Learning.

[BibT_eX]

[DOI]

Antara Ganguly

Rajeev Muralidhar

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Securing Scan through Plain-text Restriction.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Freeflow Core: Enhancing Performance of In-Order Cores with Energy Efficiency.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Preventing Scan Attack through Test Response Encryption.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Asian Test Symposium, 2019

Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design.

[BibT_eX]

[DOI]

J. Electron. Test., 2018

Memory-system requirements for convolutional neural networks.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2018

Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

On Securing Scan Design Through Test Vector Encryption.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

In-situ Monitoring for Slack Time Violation Without Performance Penalty.

[BibT_eX]

[DOI]

Nihar Hage

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A PAM-4 10S/12S line coding scheme with equi-probable levels.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging.

[BibT_eX]

[DOI]

Kanad Basu

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

AB-Aware: Application Behavior Aware Management of Shared Last Level Caches.

[BibT_eX]

[DOI]

Suhit Pai

Newton Singh

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

ATPG power guards: On limiting the test power below threshold.

[BibT_eX]

[DOI]

Rohini Gulve

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging.

[BibT_eX]

[DOI]

J. Electron. Test., 2017

A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

On Testing of Superscalar Processors in Functional Mode for Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Improving post-silicon error detection with topological selection of trace signals.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Identifying high variability speed-limiting paths under aging.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Testing multiple stuck-at faults of ROBDD based combinational circuit design.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Post-silicon observability enhancement with topology based trace signal selection.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Exploiting path delay test generation to develop better TDF tests for small delay defects.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2017

A low cost technique for scan chain diagnosis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Test pattern generation to detect multiple faults in ROBDD based combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Instruction-based self-test for delay faults maximizing operating temperature.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Revisiting random access scan for effective enhancement of post-silicon observability.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

RTL level trace signal selection and coverage estimation during post-silicon validation.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

EEAL: Processors' Performance Enhancement Through Early Execution of Aliased Loads.

[BibT_eX]

[DOI]

Abhishek Rajgadia

Newton

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Combining Restorability and Error Detection Ability for Effective Trace Signal Selection.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Achieving full functional coverage for the forwarding unit of pipelined processors.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

PHP: Power hungry pattern generation at higher abstraction level.

[BibT_eX]

[DOI]

Rohini Gulve

Anshu Goel

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

An efficient test technique to prevent scan-based side-channel attacks.

[BibT_eX]

[DOI]

Darshit Vaghani

Proceedings of the 22nd IEEE European Test Symposium, 2017

REMORA: A hybrid low-cost soft-error reliable fault tolerant architecture.

[BibT_eX]

[DOI]

Shoba Gopalakrishnan

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Preventing scan-based side-channel attacks through key masking.

[BibT_eX]

[DOI]

Darshit Vaghani

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

On Securing Scan Design from Scan-Based Side-Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture.

[BibT_eX]

[DOI]

Shoba Gopalakrishnan

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

A high performance scan flip-flop design for serial and mixed mode scan test.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

ROBDD based path delay fault testable combinational circuit synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

A trace signal selection algorithm for improved post-silicon debug.

[BibT_eX]

[DOI]

Ankit Jindal

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

ILP based don't care bits filling technique for reducing capture power.

[BibT_eX]

[DOI]

Rohini Gulve

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Performance modelling of heterogeneous ISA multicore architectures.

[BibT_eX]

[DOI]

Rameshwar Prasad Meghwal

Kuldeep Sharma

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Enabling LOS delay test with slow scan enable.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015

PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Application behavior aware re-reference interval prediction for shared LLC.

[BibT_eX]

[DOI]

Parth Lathigara

Shankar Balachandran

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A Methodology for Identifying High Timing Variability Paths in Complex Designs.

[BibT_eX]

[DOI]

Adit D. Singh

Kewal K. Saluja

Proceedings of the 24th IEEE Asian Test Symposium, 2015

A Soft Error Resilient Low Leakage SRAM Cell Design.

[BibT_eX]

[DOI]

Adithyalal P. M

Shankar Balachandran

Proceedings of the 24th IEEE Asian Test Symposium, 2015

A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

Operand Isolation with Reduced Overhead for Low Power Datapath Design.

[BibT_eX]

[DOI]

Lokesh Siddhu

Amit Mishra

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Temperature aware test scheduling by modified floorplanning.

[BibT_eX]

[DOI]

Indira Rawat

M. K. Gupta

Proceedings of the 2014 East-West Design & Test Symposium, 2014

Partially programmable circuit design.

[BibT_eX]

[DOI]

Sergey Ostanin

Irina Kirienko

Proceedings of the 2014 East-West Design & Test Symposium, 2014

A data-driven adaptive model-identification based large-scale sensor management system: Application to self powered neutron detectors.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Conference on Evolving and Adaptive Intelligent Systems, 2014

2013

Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs.

[BibT_eX]

[DOI]

Sergey A. Ostanin

Autom. Remote. Control., 2013

Tutorial T10: Post - Silicon Validation, Debug and Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP.

[BibT_eX]

[DOI]

Deepak Malani

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Scheduling tests for 3D SoCs with temperature constraints.

[BibT_eX]

[DOI]

Indira Rawat

M. K. Gupta

Proceedings of the East-West Design & Test Symposium, 2013

Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques.

[BibT_eX]

[DOI]

Sergey Ostanin

Alexey Melnikov

Proceedings of the East-West Design & Test Symposium, 2013

PDF testability of the circuits derived by special covering ROBDDs with gates.

[BibT_eX]

[DOI]

Ekaterina Nikolaeva

Dmitry Kudin

Proceedings of the East-West Design & Test Symposium, 2013

Delay testable sequential circuit designs.

[BibT_eX]

[DOI]

Eugeniy Mitrofanov

Proceedings of the East-West Design & Test Symposium, 2013

Thermal analysis and modeling of 3D integrated circuits for test scheduling.

[BibT_eX]

[DOI]

Indira Rawat

M. K. Gupta

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

Derating based hardware optimizations in soft error tolerant designs.

[BibT_eX]

[DOI]

V. Prasanth

Rubin A. Parekhji

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits.

[BibT_eX]

[DOI]

Deepak Malani

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

SEU Tolerant Robust Latch Design.

[BibT_eX]

[DOI]

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Efficient regular expression pattern matching for network intrusion detection systems using modified word-based automata.

[BibT_eX]

[DOI]

Pawan Kumar

Proceedings of the 5th International Conference of Security of Information and Networks, 2012

Impact of process variations on computers used for image processing.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

SEU tolerant robust memory cell design.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

2011

Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

C-Routing: An adaptive hierarchical NoC routing methodology.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Tutorial: "Post silicon debug of SOC designs".

[BibT_eX]

[DOI]

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Testing linear and non-linear analog circuits using moment generating functions.

[BibT_eX]

[DOI]

Proceedings of the 12th Latin American Test Workshop, 2011

SEU tolerant SRAM cell.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Reduced overhead soft error mitigation using error control coding techniques.

[BibT_eX]

[DOI]

V. Prasanth

Rubin A. Parekhji

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Parallelizing TUNAMI-N1 Using GPGPU.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011

Selection of the state variables for partial enhanced scan techniques.

[BibT_eX]

[DOI]

Alexey Melnikov

Ruslan Mukhamedov

Proceedings of the 9th East-West Design & Test Symposium, 2011

Level of confidence evaluation and its usage for Roll-back Recovery with Checkpointing optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011

GA Based Congestion Aware Topology Generation for Application Specific NoC.

[BibT_eX]

[DOI]

Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

Test and Diagnosis of Analog Circuits Using Moment Generating Functions.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

SSTKR: Secure and Testable Scan Design through Test Key Randomization.

[BibT_eX]

[DOI]

Mohammed Abdul Razzaq

Adit D. Singh

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

On Minimization of Test Application Time for RAS.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Genetic algorithm based topology generation for application specific Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Test application time minimization for RAS using basis optimization of column decoder.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Robust detection of soft errors using delayed capture methodology.

[BibT_eX]

[DOI]

V. Prasanth

Rubin A. Parekhji

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Graph theoretic approach for scan cell reordering to minimize peak shift power.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Energy-efficient redundant execution for chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

SEU tolerant SRAM for FPGA applications.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

Fault grading using Instruction-Execution graph.

[BibT_eX]

[DOI]

K. R. Vinutha

Manoj Singh Gaur

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Thermal aware test scheduling for stacked multi-chip-modules.

[BibT_eX]

[DOI]

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Path delay faults and ENF.

[BibT_eX]

[DOI]

Valeriy B. Lipsky

Alexey Melnikov

Proceedings of the 2010 East-West Design & Test Symposium, 2010

FREP: A soft error resilient pipelined RISC architecture.

[BibT_eX]

[DOI]

Viney Kumar

Rahul Raj Choudhary

Proceedings of the 2010 East-West Design & Test Symposium, 2010

On selection of state variables for delay test of identical functional units.

[BibT_eX]

[DOI]

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Modified T-Flip-Flop based scan cell for RAS.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010

Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing.

[BibT_eX]

[DOI]

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Modified Scan Flip-Flop for Low Power Testing.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Polynomial coefficient based DC testing of non-linear analog circuits.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

DX-compactor: distributed X-compaction for SoCs.

[BibT_eX]

[DOI]

Reshma C. Jumani

Niraj Bharatkumar Jain

Kewal K. Saluja

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

On Minimization of Peak Power for Scan Circuit during Test.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE European Test Symposium, 2009

Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips.

[BibT_eX]

[DOI]

Mikael Väyrynen

Erik Larsson

Proceedings of the Design, Automation and Test in Europe, 2009

Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients.

[BibT_eX]

[DOI]