Bruce Querbach

According to our database1, Bruce Querbach authored at least 4 papers between 2013 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC.
IEEE Des. Test, 2016

2015
Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine.
Proceedings of the 2015 IEEE International Test Conference, 2015

2014
A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time.
Proceedings of the 2014 International Test Conference, 2014

2013
Comparison of hardware based and software based stress testing of memory IO interface.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013


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