Bruno Ferres

According to our database, Bruno Ferres authored at least 7 papers between 2020 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance Versus Precision Tradeoffs.

Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian Ghadikolaei

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2026

2025

A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits.

Bruno Ferres, Oussama Oulkaid, Matthieu Moy, Gabriel Radanne, Ludovic Henrio, Pascal Raymond, Mehdi Khosravian

ACM Trans. Design Autom. Electr. Syst., September, 2025

2024

A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving.

Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

A Chisel Framework for Flexible Design Space Exploration through a Functional Approach.

Bruno Ferres, Olivier Muller, Frédéric Rousseau

ACM Trans. Design Autom. Electr. Syst., July, 2023

Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory.

Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian Ghadikolaei, Matthieu Moy, Gabriel Radanne, Pascal Raymond

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2021

Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration.

Bruno Ferres, Olivier Muller, Frédéric Rousseau

Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021

2020

Chisel Usecase: Designing General Matrix Multiply for FPGA.

Bruno Ferres, Olivier Muller, Frédéric Rousseau

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020