Burak Unal

Orcid: 0000-0002-9357-5879

According to our database1, Burak Unal authored at least 7 papers between 2016 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Low-Density Parity-Check Code Decoder Design and Error Characterization on an FPGA Based Framework.
PhD thesis, 2019

Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC Codes.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Accelerated Shadow Detection and Removal Method.
Proceedings of the 16th IEEE/ACS International Conference on Computer Systems and Applications, 2019

2018
Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
Analysis and implementation of resource efficient probabilistic Gallager B LDPC decoder.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Efficient FPGA implementation of probabilistic gallager B LDPC decoder.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
Resource efficient real-time processing of Contrast Limited Adaptive Histogram Equalization.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016


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