Khoa Le

Orcid: 0000-0001-6006-5920

According to our database1, Khoa Le authored at least 24 papers between 2012 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2021
Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

An Enhanced Check-Node Architecture for 5G New Radio LDPC Decoders.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020
The SPIR: An Autonomous Underwater Robot for Bridge Pile Cleaning and Condition Assessment.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2020

2019
Simultaneous Feature Aggregating and Hashing for Compact Binary Code Learning.
IEEE Trans. Image Process., 2019

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Performance Enhancement of Polar Codes in Multi-level Cell NAND Flash Memories using Systematic Encoding.
Proceedings of the 19th International Symposium on Communications and Information Technologies, 2019

A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes.
Proceedings of the 19th International Symposium on Communications and Information Technologies, 2019

Demo Abstract: An End-to-End Real-Time Efficient System for Smart Energy Monitoring.
Proceedings of the IEEE INFOCOM 2019, 2019

2018
Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

The Probabilistic Finite Alphabet Iterative Decoder for Low-Density Parity-Check Codes.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

On the use of Probabilistic Parallel Bit-Flipping decoder for the storage systems.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

On the Use of Hard-Decision LDPC Decoders on MLC NAND Flash Memory.
Proceedings of the 15th International Multi-Conference on Systems, Signals & Devices, 2018

2017
Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Efficient FPGA implementation of probabilistic gallager B LDPC decoder.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Mining Software Engineering Team Project Work Logs to Generate Formative Assessment.
Proceedings of the 24th Asia-Pacific Software Engineering Conference Workshops, 2017

2016
Non-surjective finite alphabet iterative decoders.
Proceedings of the 2016 IEEE International Conference on Communications, 2016

2015
FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Efficient realization of probabilistic gradient descent bit flipping decoders.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013
Detecting stepping-stones under the influence of packet jittering.
Proceedings of the 9th International Conference on Information Assurance and Security, 2013

2012
Polarization in Wireless Communications.
Phys. Commun., 2012

Energy efficient hybrid display and predictive models for embedded and mobile systems.
Proceedings of the 15th International Conference on Compilers, 2012


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