C. André T. Salama

According to our database1, C. André T. Salama authored at least 39 papers between 1964 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2007
A low-power CSCD asynchronous viterbi decoder for wireless applications.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2005
8 GHz tunable CMOS quadrature generator using differential active inductors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology.
IEEE J. Solid State Circuits, 2004

CMOS wireless phase-shifted transmitter.
IEEE J. Solid State Circuits, 2004

CMOS phase shifted transmitters for 4G wireless systems.
Proceedings of the IEEE 15th International Symposium on Personal, 2004

Low-power asynchronous viterbi decoder for wireless applications.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003
Energy Efficient Adiabatic Multiplier-Accumulator Design.
J. VLSI Signal Process., 2003

An 8-bit 2-GSample/s analog-to-digital converter in 0.5µm SiGe technology.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 10Gb/s CDR with a half-rate bang-bang phase detector.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A novel C-band CMOS phase shifter for communication systems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 1 V, 8 GHz CMOS integrated phase shifted transmitter for wideband and varying envelope communication systems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
A bipolar 2-GSample/s track-and-hold amplifier (THA) in 0.35 μm SiGe technology.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
1 V, 1.9 GHz mixer using a lateral bipolar transistor in CMOS.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

An improved bang-bang phase detector for clock and data recovery applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A 10 bit, 50 M sample/s, low power pipelined A/D converter for cable modem applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications.
IEEE J. Solid State Circuits, 2000

A pipelined multiply-accumulate unit design for energy recovery DSP systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS.
IEEE J. Solid State Circuits, 1999

Differential 0.35µm CMOS circuits for 622 MHz/933 MHz monolithic clock and data recovery applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Giga bit per second per pin differential CMOS circuits for pseudo ECL signaling.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
Integration of a short-loop SLIC in a low-voltage submicron BiCMOS technology.
IEEE J. Solid State Circuits, 1998

High-speed ECL-compatible serial I/O in 0.35 μm CMOS.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP Systems.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997
Phase-correcting feedback system for class E power amplifier.
IEEE J. Solid State Circuits, 1997

1996
GaAs dynamic memory design.
IEEE J. Solid State Circuits, 1996

GaAs Schmitt trigger memory cell design.
IEEE J. Solid State Circuits, 1996

1995
Low voltage, high efficiency GaAs Class E power amplifiers for wireless transmitters.
IEEE J. Solid State Circuits, October, 1995

Linear transmitter design using high efficiency Class E power amplifier.
Proceedings of the 6th IEEE International Symposium on Personal, 1995

1994
GaAs split phase dynamic logic.
IEEE J. Solid State Circuits, May, 1994

Low-Power Current-Mode Algorithmic ADC.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Voltage Gain Enhancement by Conductance Cancellation in GaAs MESFET Opamps.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A 10 Bit Semi-Algorithmic Current Mode DAC.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992
A novel technique for image-velocity computation.
IEEE Trans. Circuits Syst. Video Technol., 1992

An imager with built-in image-velocity computation capability.
IEEE Trans. Circuits Syst. Video Technol., 1992

1991
GaAs pipelined dynamic logic.
Integr., 1991

1989
A microprogrammable processor using single poly EPROM.
Integr., 1989

1987
Improved Simulation of p- and n-channel MOSFET's Using an Enhanced SPICE MOS3 Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

Expandable arithmetic block macrocell.
Integr., 1987

1964
Series Connected Tunnel-Diode Multilevel Register.
IEEE Trans. Electron. Comput., 1964


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