David Nairn

Affiliations:
  • University of Waterloo


According to our database1, David Nairn authored at least 17 papers between 1994 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A Simple Wireless Sensor Node System for Electricity Monitoring Applications: Design, Integration, and Testing with Different Piezoelectric Energy Harvesters.
Sensors, 2018

2017
Design and development of a self-contained and non-invasive integrated system for electricity monitoring applications.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Analog integrated circuit design using fixed-length devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2013
Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow.
IEEE Trans. Very Large Scale Integr. Syst., 2013

An Energy-Efficient Offset-Cancelling Sense Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

2012
Cascode Loads and Amplifier Settling Behavior.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

2011
A parametric DFM solution for analog circuits: Electrical driven hot spot detection, analysis and correction flow.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Design and analysis of metastable-hardened flip-flops in sub-threshold region.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

An electrical-aware parametric DFM solution for analog circuits.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

2010
A low power 12-bit 10MS/s algorithmic ADC.
Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering, 2010

2008
Time-interleaved analog-to-digital converters.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2005
Data converters.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2000
A 10-bit, 3 V, 100 MS/s pipelined ADC.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1995
Optimizing the Performance of Switched Current Circuits.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Zero-Voltage Switching in Switched Current Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


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