Hormoz Djahanshahi

According to our database1, Hormoz Djahanshahi authored at least 15 papers between 1996 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A Compact Dual-Core 26.1-to-29.9GHz Coupled-CMOS LC-VCO with Implicit Common-Mode Resonance and FoM of-191 dBc/Hz at 10MHz.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2018
On the Design of Vertical-Turn Solenoids for Magnetically Isolated Densely Integrated LC Oscillators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A SEE Insensitive CML Voltage Controlled Oscillator in 65nm CMOS.
Proceedings of the 2018 IEEE Canadian Conference on Electrical & Computer Engineering, 2018

A Hardened-By-Design Technique for LC-Tank Voltage Controlled Oscillator.
Proceedings of the 2018 IEEE Canadian Conference on Electrical & Computer Engineering, 2018

2016
On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise.
IEEE J. Solid State Circuits, 2016

2013
Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration.
J. Electr. Comput. Eng., 2013

2012
Design and verification of integrated inductors in CMOS.
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

2011
A 27-GHz low-power push-push LC VCO with wide tuning range in 65nm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2006
Modeling and Characterization of VCOs with MOS Varactors for RF Transceivers.
EURASIP J. Wirel. Commun. Netw., 2006

2005
Modeling of MOS varactors and characterizing the tuning curve of a 5-6 GHz LC VCO.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

1999
Differential 0.35µm CMOS circuits for 622 MHz/933 MHz monolithic clock and data recovery applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Neural Network Integrated Circuits with Single-Block Mixed Signal Arrays.
J. Circuits Syst. Comput., 1998

A Low-Variation Nonlinear Neuron Circuit.
J. Circuits Syst. Comput., 1998

1996
A modular architecture for hybrid VLSI neural networks and its application in a smart photosensor.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996

Design and VLSI Implementation of a Unified Synapse-Neuron Architecture.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996


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