Carlos E. Muñoz

According to our database, Carlos E. Muñoz authored at least 5 papers between 2005 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration.

Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer

IEEE J. Solid State Circuits, 2014

11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR.

Dong-Young Chang, Carlos E. Muñoz, Denis C. Daly, Soon-Kyun Shin, Kevin Guay, Thomas Thurston, Hae-Seung Lee, Kush Gulati, Matthew Z. Straayer

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS.

Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2006

A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs.

Kush Gulati, Mark Peng, Anurag Pulincherry, Carlos E. Muñoz, Mike Lugin, Alex R. Bugeja, Jipeng Li, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2006

2005

A highly-integrated CMOS analog baseband transceiver with 180MSPS 13b pipelined CMOS ADC and dual 12b DACs.

Kush Gulati, Mark Peng, Anurag Pulincherry, Carlos E. Muñoz, Mike Lugin, Alex R. Bugeja, Jipeng Li, Anantha P. Chandrakasan

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005