Jipeng Li

According to our database1, Jipeng Li authored at least 17 papers between 2002 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


Industry Chain Graph Building Based on Text Semantic Association Mining.
Proceedings of the International Joint Conference on Neural Networks, 2021

Feature Pyramid Attention Model and Multi-Label Focal Loss for Pedestrian Attribute Recognition.
IEEE Access, 2020

Ferryman at SemEval-2020 Task 12: BERT-Based Model with Advanced Improvement Methods for Multilingual Offensive Language Identification.
Proceedings of the Fourteenth Workshop on Semantic Evaluation, 2020

Ferryman at SemEval-2020 Task 7: Ensemble Model for Assessing Humor in Edited News Headlines.
Proceedings of the Fourteenth Workshop on Semantic Evaluation, 2020

Optimal Defense Strategy against Evasion Attacks.
Proceedings of the 16th International Conference on Mobility, Sensing and Networking, 2020

Dynamic Simulation of the Vehicle/Bridge Coupled System in High-Temperature Superconducting Maglev.
Comput. Sci. Eng., 2019

A 2 GS/s 14-bit current-steering DAC in 65 nm CMOS technology for wireless transmitter.
IEICE Electron. Express, 2018

High-Temperature Superconducting Magnetic Levitation Vehicles: Dynamic Characteristics While Running on a Ring Test Line.
IEEE Veh. Technol. Mag., 2017

The Mapping-Adaptive Convolution: A Fundamental Theory for Homography or Perspective Invariant Matching Methods.
SIAM J. Imaging Sci., 2017

Low-Power and High-Speed Pipelined ADC Using Time-Aligned CDS Technique.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC".
IEEE J. Solid State Circuits, 2006

A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs.
IEEE J. Solid State Circuits, 2006

A highly-integrated CMOS analog baseband transceiver with 180MSPS 13b pipelined CMOS ADC and dual 12b DACs.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Radix-based digital calibration techniques for multi-stage recycling pipelined ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Background calibration techniques for multistage pipelined ADCs with digital redundancy.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

An extended radix-based digital calibration technique for multi-stage ADC.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

High-speed pipelined A/D converter using time-shifted CDS technique.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002