César Torres-Huitzil

Moisés Arredondo-Velázquez

Neural Comput. Appl., 2020

A streaming architecture for Convolutional Neural Networks based on layer operations chaining.

[BibT_eX]

[DOI]

Javier Díaz-Carmona

José Alfredo Padilla-Medina

Juan Prado-Olivarez

J. Real Time Image Process., 2020

Smartphone-Based Remote Monitoring Tool for e-Learning.

[BibT_eX]

[DOI]

Carmen Carlota Martinez-Gil

Jorge de la Calleja

Alan Díaz-Manríquez

IEEE Access, 2020

2019

A Spatio-Temporal Approach to Individual Mobility Modeling in On-Device Cognitive Computing Platforms.

[BibT_eX]

[DOI]

Sensors, 2019

A Cognitive-Inspired Event-Based Control for Power-Aware Human Mobility Analysis in IoT Devices.

[BibT_eX]

[DOI]

Moisés Arredondo-Velázquez

Sensors, 2019

A streaming accelerator of Convolutional Neural Networks for resource-limited applications.

[BibT_eX]

[DOI]

Javier Díaz-Carmona

Alejandro Israel Barranco Gutiérrez

José Alfredo Padilla-Medina

Juan Prado-Olivarez

IEICE Electron. Express, 2019

2018

On-Device Learning of Indoor Location for WiFi Fingerprint Approach.

[BibT_eX]

[DOI]

Hiram Herrera-Rivas

Heidy Marisol Marín Castro

Yuriria Coronado-Pérez

Sensors, 2018

An On-Device Cognitive Dynamic Systems Inspired Sensing Framework for the IoT.

[BibT_eX]

[DOI]

IEEE Commun. Mag., 2018

Evaluation of the Impact of Data Uncertainty on the Prediction of Physiological Patient Deterioration.

[BibT_eX]

[DOI]

Josue Reyes-Garcia

Alejandro Galaviz-Mosqueda

IEEE Access, 2018

2017

Fault and Error Tolerance in Neural Networks: A Review.

[BibT_eX]

[DOI]

IEEE Access, 2017

Fault tolerance of self organizing maps.

[BibT_eX]

[DOI]

Oleksandr V. Popovych

Proceedings of the 12th International Workshop on Self-Organizing Maps and Learning Vector Quantization, 2017

Fault tolerance in neural networks: Neural design and hardware implementation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Optimal weight storage improves fault tolerance of SOMs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

2016

Full On-Device Stay Points Detection in Smartphones for Location-Based Mobile Applications.

[BibT_eX]

[DOI]

Sensors, 2016

Power management techniques in smartphone-based mobility sensing systems: A survey.

[BibT_eX]

[DOI]

Pervasive Mob. Comput., 2016

FPGA-based fast computation of gray-level morphological granulometries.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2016

Event based visual attention with dynamic neural field on FPGA.

[BibT_eX]

[DOI]

Benoît Chappet de Vangel

Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

2015

Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

Randomly Spiking Dynamic Neural Fields.

[BibT_eX]

[DOI]

Benoit Chappet de Vangel

Pedro Alberto Cerna-Garcia

ACM J. Emerg. Technol. Comput. Syst., 2015

A CPG system based on spiking neurons for hexapod robot locomotion.

[BibT_eX]

[DOI]

Horacio Rostro-González

Gerardo Trejo-Caballero

Carlos H. Garcia-Capulin

Mario Alberto Ibarra-Manzano

Juan Gabriel Aviña-Cervantes

Neurocomputing, 2015

Perception-driven adaptive CPG-based locomotion for hexapod robots.

[BibT_eX]

[DOI]

Neurocomputing, 2015

Robust smartphone-based human activity recognition using a tri-axial accelerometer.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Stochastic and asynchronous spiking dynamic neural fields.

[BibT_eX]

[DOI]

Benoit Chappet de Vangel

Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

2014

Areatime Efficient Implementation of Local Adaptive Image Thresholding in Reconfigurable Hardware.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2014

Mobile Phone Middleware Architecture for Energy and Context Awareness in Location-Based Services.

[BibT_eX]

[DOI]

Javier Rubio-Loyola

Sensors, 2014

Fast hardware architecture for grey-level image morphology with flat structuring elements.

[BibT_eX]

[DOI]

IET Image Process., 2014

Spiking dynamic neural fields architectures on FPGA.

[BibT_eX]

[DOI]

Benoit Chappet de Vangel

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Versatile educational and research robotic platform based on reconfigurable hardware.

[BibT_eX]

[DOI]

Carlos Andres Lara-Nino

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

FPGA-based real-time citrus classification system.

[BibT_eX]

[DOI]

Josue Jimenez-Arteaga

Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Embedded Image Processing System for Automatic Page Segmentation of Open Book Images.

[BibT_eX]

[DOI]

Victor Rodríguez-Osoria

Proceedings of the Advances in Visual Computing - 10th International Symposium, 2014

2013

FPGA implementation of a configurable neuromorphic CPG-based locomotion controller.

[BibT_eX]

[DOI]

Neural Networks, 2013

On an external memory scheme for processor arrays.

[BibT_eX]

[DOI]

Juan M. Campos

IEICE Electron. Express, 2013

Processor arrays generation for matrix algorithms used in embedded platforms.

[BibT_eX]

[DOI]

Lorenzo Antonio Delgado-Guillen

Juan M. Campos

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Digital watermarking of color images utilizing mobile platforms.

[BibT_eX]

[DOI]

Jose Juan Garcia-Hernandez

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Hardware realization of a lightweight 2D cellular automata-based cipher for image encryption.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2012

Comparison between 2D cellular automata based pseudorandom number generators.

[BibT_eX]

[DOI]

Marco Delgadillo-Escobar

IEICE Electron. Express, 2012

Versatile FPGA-based locomotion platform for legged robots.

[BibT_eX]

[DOI]

Horacio Rostro-González

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

A Hardware Architecture for Image Clustering Using Spiking Neural Networks.

[BibT_eX]

[DOI]

Héctor Hugo Avilés-Arriaga

Miguel Morales-Sandoval

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

An FPGA-based approach for parameter estimation in spiking neural networks.

[BibT_eX]

[DOI]

Horacio Rostro-González

Guillaume Garreau

Andreas G. Andreou

Julius Georgiou

Lorenzo Antonio Delgado-Guillen

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Validating the existence of watermarks on digital images using a mobile phone.

[BibT_eX]

[DOI]

Jose Juan Garcia-Hernandez

Proceedings of the 7th International Conference for Internet Technology and Secured Transactions, 2012

FPGA implementation of Pseudorandom Number Generators with a generic 2-D cellular automata architecture.

[BibT_eX]

[DOI]

Marco Delgadillo-Escobar

Proceedings of the 22nd International Conference on Electrical Communications and Computers, 2012

2011

FPGA-based CPG Robot Locomotion Modulation Using a Fuzzy Scheme and Visual Information.

[BibT_eX]

[DOI]

Jose Juan Garcia-Hernandez

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

On a Hybrid and General Control Scheme for Algorithms Represented as a Polytope.

[BibT_eX]

[DOI]

Juan M. Campos

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Two-phase GA parameter tunning method of CPGs for quadruped gaits.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

A Hardware Coprocessor Integrated with OpenCV for Edge Detection Using Cellular Neural Networks.

[BibT_eX]

[DOI]

Miguel Morales-Sandoval

Proceedings of the Sixth International Conference on Image and Graphics, 2011

2010

A temporal coding hardware implementation for spiking neural networks.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2010

FPGA-based Circuit for Central Pattern Generator in Quadruped Locomotion.

[BibT_eX]

[DOI]

Aust. J. Intell. Inf. Process. Syst., 2010

Hardware Implementation of a CPG-Based Locomotion Control for Quadruped Robots.

[BibT_eX]

[DOI]

Proceedings of the Artificial Neural Networks, 2010

2009

Reaction Diffusion and Chemotaxis for Decentralized Gathering on FPGAs.

[BibT_eX]

[DOI]

Nikolaos Vlassopoulos

Int. J. Reconfigurable Comput., 2009

On the Implementation of Central Pattern Generators for Periodic Rhythmic Locomotion.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Hardware implementation of Spiking Neural Network classifiers based on backpropagation-based learning algorithms.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2009

2008

Embedded Harmonic Control for Trajectory Planning in Large Environments.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Fast Implementation of a Bio-inspired Model for Decentralized Gathering.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Flexible Architecture for Three Classes of Optical Flow Extraction Algorithms.

[BibT_eX]

[DOI]

Mauricio Cerda

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity.

[BibT_eX]

[DOI]

Proceedings of the Artificial Neural Networks, 2008

Implementation of Central Pattern Generator in an FPGA-Based Embedded System.

[BibT_eX]

[DOI]

Proceedings of the Artificial Neural Networks, 2008

2007

Massively distributed digital implementation of an integrate-and-fire LEGION network for visual scene segmentation.

[BibT_eX]

[DOI]

Neurocomputing, 2007

High Performance Hardware Implementation of SpikeProp Learning: Potential and Tradeoffs.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Hardware/Software Codesign for Embedded Implementation of Neural Networks.

[BibT_eX]

[DOI]

Adrien Gauffriau

Proceedings of the Reconfigurable Computing: Architectures, 2007

2006

A Bit-Stream Pulse-Based Digital Neuron Model for Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Neural Information Processing, 13th International Conference, 2006

Area-Efficient Implementation of a Pulse-Mode Neuron Model.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA implementation of an integrate-and-fire LEGION model for image segmentation.

[BibT_eX]

[DOI]

Proceedings of the 14th European Symposium on Artificial Neural Networks, 2006

2005

On-chip visual perception of motion: A bio-inspired connectionist model on FPGA.

[BibT_eX]

[DOI]

Claudio Castellanos Sánchez

Neural Networks, 2005

FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2005

FPGA Implementation of an Excitatory and Inhibitory Connectionist Model for Motion Perception.

[BibT_eX]

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2004

Real-time image processing with a compact FPGA-based systolic architecture.

[BibT_eX]

[DOI]

Real Time Imaging, 2004

Design and Implementation of a CFAR Processor for Target Detection.

[BibT_eX]

[DOI]

René Cumplido-Parra

Santos López-Estrada

Proceedings of the Field Programmable Logic and Application, 2004

A Hybrid Approach for Target Detection Using CFAR Algorithm and Image Processing.

[BibT_eX]

[DOI]

Santos López-Estrada

René Cumplido-Parra

Proceedings of the 5th Mexican International Conference on Computer Science (ENC 2004), 2004

2003

Configurable Hardware Architecture for Real-Time Window-Based Image Processing.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002

A reconfigurable vision system for real-time applications.

[BibT_eX]

[DOI]

Selene Maya-Rueda

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

2001

Real-time field programmable gate array architecture for computer vision.

[BibT_eX]

[DOI]

J. Electronic Imaging, 2001

2000

Compact Spiking Neural Network Implementation in FPGA.

[BibT_eX]

[DOI]

Selene Maya

M. Rocio Reynoso

Proceedings of the Field-Programmable Logic and Applications, 2000

An FPGA Architecture for High Speed Edge and Corner Detection.

[BibT_eX]

[DOI]