César Torres-Huitzil

According to our database1, César Torres-Huitzil authored at least 67 papers between 2000 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A Spatio-Temporal Approach to Individual Mobility Modeling in On-Device Cognitive Computing Platforms.
Sensors, 2019

A Cognitive-Inspired Event-Based Control for Power-Aware Human Mobility Analysis in IoT Devices.
Sensors, 2019

2018
On-Device Learning of Indoor Location for WiFi Fingerprint Approach.
Sensors, 2018

An On-Device Cognitive Dynamic Systems Inspired Sensing Framework for the IoT.
IEEE Communications Magazine, 2018

Evaluation of the Impact of Data Uncertainty on the Prediction of Physiological Patient Deterioration.
IEEE Access, 2018

2017
Fault and Error Tolerance in Neural Networks: A Review.
IEEE Access, 2017

Fault tolerance of self organizing maps.
Proceedings of the 12th International Workshop on Self-Organizing Maps and Learning Vector Quantization, 2017

Fault tolerance in neural networks: Neural design and hardware implementation.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Optimal weight storage improves fault tolerance of SOMs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

2016
Full On-Device Stay Points Detection in Smartphones for Location-Based Mobile Applications.
Sensors, 2016

Power management techniques in smartphone-based mobility sensing systems: A survey.
Pervasive and Mobile Computing, 2016

FPGA-based fast computation of gray-level morphological granulometries.
J. Real-Time Image Processing, 2016

Event based visual attention with dynamic neural field on FPGA.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

2015
Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Randomly Spiking Dynamic Neural Fields.
JETC, 2015

A CPG system based on spiking neurons for hexapod robot locomotion.
Neurocomputing, 2015

Perception-driven adaptive CPG-based locomotion for hexapod robots.
Neurocomputing, 2015

Robust smartphone-based human activity recognition using a tri-axial accelerometer.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Stochastic and asynchronous spiking dynamic neural fields.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

2014
Areatime Efficient Implementation of Local Adaptive Image Thresholding in Reconfigurable Hardware.
SIGARCH Computer Architecture News, 2014

Mobile Phone Middleware Architecture for Energy and Context Awareness in Location-Based Services.
Sensors, 2014

Fast hardware architecture for grey-level image morphology with flat structuring elements.
IET Image Processing, 2014

Spiking dynamic neural fields architectures on FPGA.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Versatile educational and research robotic platform based on reconfigurable hardware.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

FPGA-based real-time citrus classification system.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Embedded Image Processing System for Automatic Page Segmentation of Open Book Images.
Proceedings of the Advances in Visual Computing - 10th International Symposium, 2014

2013
FPGA implementation of a configurable neuromorphic CPG-based locomotion controller.
Neural Networks, 2013

On an external memory scheme for processor arrays.
IEICE Electronic Express, 2013

Processor arrays generation for matrix algorithms used in embedded platforms.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

2012
Comparison between 2D cellular automata based pseudorandom number generators.
IEICE Electronic Express, 2012

Versatile FPGA-based locomotion platform for legged robots.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

A Hardware Architecture for Image Clustering Using Spiking Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

An FPGA-based approach for parameter estimation in spiking neural networks.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Validating the existence of watermarks on digital images using a mobile phone.
Proceedings of the 7th International Conference for Internet Technology and Secured Transactions, 2012

FPGA implementation of Pseudorandom Number Generators with a generic 2-D cellular automata architecture.
Proceedings of the 22nd International Conference on Electrical Communications and Computers, 2012

2011
FPGA-based CPG Robot Locomotion Modulation Using a Fuzzy Scheme and Visual Information.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

On a Hybrid and General Control Scheme for Algorithms Represented as a Polytope.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Two-phase GA parameter tunning method of CPGs for quadruped gaits.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

A Hardware Coprocessor Integrated with OpenCV for Edge Detection Using Cellular Neural Networks.
Proceedings of the Sixth International Conference on Image and Graphics, 2011

2010
A temporal coding hardware implementation for spiking neural networks.
SIGARCH Computer Architecture News, 2010

FPGA-based Circuit for Central Pattern Generator in Quadruped Locomotion.
Austr. J. Intelligent Information Processing Systems, 2010

Hardware Implementation of a CPG-Based Locomotion Control for Quadruped Robots.
Proceedings of the Artificial Neural Networks, 2010

2009
Reaction Diffusion and Chemotaxis for Decentralized Gathering on FPGAs.
Int. J. Reconfig. Comp., 2009

On the Implementation of Central Pattern Generators for Periodic Rhythmic Locomotion.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Hardware implementation of Spiking Neural Network classifiers based on backpropagation-based learning algorithms.
Proceedings of the International Joint Conference on Neural Networks, 2009

2008
Embedded Harmonic Control for Trajectory Planning in Large Environments.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Fast Implementation of a Bio-inspired Model for Decentralized Gathering.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Flexible Architecture for Three Classes of Optical Flow Extraction Algorithms.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity.
Proceedings of the Artificial Neural Networks, 2008

Implementation of Central Pattern Generator in an FPGA-Based Embedded System.
Proceedings of the Artificial Neural Networks, 2008

2007
Massively distributed digital implementation of an integrate-and-fire LEGION network for visual scene segmentation.
Neurocomputing, 2007

High Performance Hardware Implementation of SpikeProp Learning: Potential and Tradeoffs.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Hardware/Software Codesign for Embedded Implementation of Neural Networks.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
A Bit-Stream Pulse-Based Digital Neuron Model for Neural Networks.
Proceedings of the Neural Information Processing, 13th International Conference, 2006

Area-Efficient Implementation of a Pulse-Mode Neuron Model.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA implementation of an integrate-and-fire LEGION model for image segmentation.
Proceedings of the ESANN 2006, 2006

2005
On-chip visual perception of motion: A bio-inspired connectionist model on FPGA.
Neural Networks, 2005

FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing.
EURASIP J. Adv. Sig. Proc., 2005

FPGA Implementation of an Excitatory and Inhibitory Connectionist Model for Motion Perception.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2004
Real-time image processing with a compact FPGA-based systolic architecture.
Real-Time Imaging, 2004

Design and Implementation of a CFAR Processor for Target Detection.
Proceedings of the Field Programmable Logic and Application, 2004

A Hybrid Approach for Target Detection Using CFAR Algorithm and Image Processing.
Proceedings of the 5th Mexican International Conference on Computer Science (ENC 2004), 2004

2003
Configurable Hardware Architecture for Real-Time Window-Based Image Processing.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
A reconfigurable vision system for real-time applications.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

2001
Real-time field programmable gate array architecture for computer vision.
J. Electronic Imaging, 2001

2000
Compact Spiking Neural Network Implementation in FPGA.
Proceedings of the Field-Programmable Logic and Applications, 2000

An FPGA Architecture for High Speed Edge and Corner Detection.
Proceedings of the Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), 2000


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