Chang Hyun Park

Orcid: 0000-0002-8250-8574

Affiliations:
  • Uppsala University, Department of Information Technology, Uppsala, Sweden
  • Korea Advanced Institute of Science and Technology (KAIST), School of Computing, Daejeon, Republic of Korea (PhD 2019)


According to our database1, Chang Hyun Park authored at least 22 papers between 2014 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
It's Not the Storage: Exposing Linux Kernel Bottlenecks in Page Fault Handling on NVMe SSD-backed Systems.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2026

CoGraf: Fully Accelerating Graph Applications with Fine-Grained PIM.
Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2026

2025
Accelerating Page Migrations in Operating Systems With Intel DSA.
IEEE Comput. Archit. Lett., 2025

Pimba: A Processing-in-Memory Acceleration for Post-Transformer Large Language Model Serving.
Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025

2023
Exploring the Latency Sensitivity of Cache Replacement Policies.
IEEE Comput. Archit. Lett., 2023

Large-scale Graph Processing on Commodity Systems: Understanding and Mitigating the Impact of Swapping.
Proceedings of the International Symposium on Memory Systems, 2023

Protean: Resource-efficient Instruction Prefetching.
Proceedings of the International Symposium on Memory Systems, 2023

2022
Supporting Dynamic Translation Granularity for Hybrid Memory Systems.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Every walk's a hit: making page walks single-access cache hits.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021
A Reusable Characterization of the Memory System Behavior of SPEC2017 and SPEC2006.
ACM Trans. Archit. Code Optim., 2021

2020
Reconciling Time Slice Conflicts of Virtual Machines With Dual Time Slice for Clouds.
IEEE Trans. Parallel Distributed Syst., 2020

Page Tables: Keeping them Flat and Hot (Cached).
CoRR, 2020

Architecturally-Independent and Time-Based Characterization of SPEC CPU 2017.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

Perforated Page: Supporting Fragmented Memory Allocation for Large Pages.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Decoupled Address Translation for Heterogeneous Memory Systems.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019
Morphable DRAM Cache Design for Hybrid Memory Systems.
ACM Trans. Archit. Code Optim., 2019

2018
Efficient Hardware-Assisted Logging with Asynchronous and Direct-Update for Persistent Memory.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Accelerating critical OS services in virtualized systems with flexible micro-sliced cores.
Proceedings of the Thirteenth EuroSys Conference, 2018

2017
Hybrid TLB Coalescing: Improving TLB Translation Coverage under Diverse Fragmented Memory Allocations.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2016
Virtual Snooping Coherence for Multi-Core Virtualized Systems.
IEEE Trans. Parallel Distributed Syst., 2016

Efficient Synonym Filtering and Scalable Delayed Translation for Hybrid Virtual Caching.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2014
Micro-Sliced Virtual Processors to Hide the Effect of Discontinuous CPU Availability for Consolidated Systems.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014


  Loading...