# Chang N. Zhang

According to our database

Collaborative distances:

^{1}, Chang N. Zhang authored at least 69 papers between 1984 and 2016.Collaborative distances:

## Timeline

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## Bibliography

2016

A new and fast cryptographic hash function based on RC4.

Cryptologia, 2016

2013

A Hybrid Fault Tolerant Approach for AES.

I. J. Network Security, 2013

RCBM: a rough content-based image quality assessment metric.

IJGCRSIS, 2013

2012

A Secure Multicast Scheme for Wireless Sensor Networks.

Proceedings of the Third FTRA International Conference on Mobile, 2012

RC4-BHF: An Improved RC4-Based Hash Function.

Proceedings of the 12th IEEE International Conference on Computer and Information Technology, 2012

2011

RC4 state and its applications.

Proceedings of the Ninth Annual Conference on Privacy, Security and Trust, 2011

2010

A lightweight secure data transmission protocol for resource constrained devices.

Security and Communication Networks, 2010

Design of Optimal Fault-Tolerant VLSI Systolic Array.

I. J. Comput. Appl., 2010

A Novel Watermarking Scheme for Blind Objective Image Quality Assessment.

I. J. Comput. Appl., 2010

An Algorithm Based Concurrent Error Detection Scheme for AES.

Proceedings of the Cryptology and Network Security - 9th International Conference, 2010

2008

Algorithm-Based Fault-Tolerant Cryptography.

Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

A criterion-based multilayer access control approach for multimedia applications and the implementation considerations.

TOMCCAP, 2008

A Security Protocol for Wireless Sensor Networks.

Proceedings of the Wireless Sensor and Actor Networks II, 2008

2006

An Approach to XML-Based Administration and Secure Information Flow Analysis on an Object Oriented Role-Based Access Control Model.

J. Inf. Sci. Eng., 2006

A Role-Based Multilevel Security Access Control Model.

JCIS, 2006

A Unified Data Secure and Fault Tolerant Approach for Distributed Computing.

I. J. Comput. Appl., 2006

A CAM Based Associative Processor Array for Parallel Implementation of AES.

I. J. Comput. Appl., 2006

An RC4 based Light Weight Secure Protocol for Sensor Networks.

Proceedings of the Sixth IASTED International Multi-Conference on Wireless and Optical Communications: Conference on Communication Systems and Applications, 2006

Quantitative Analysis and Enforcement of the Principle of Least Privilege in Role-Based.

Proceedings of the SECRYPT 2006, 2006

A Criterion-Based Role-Based Multilayer Access Control Model for Multimedia Applications.

Proceedings of the Eigth IEEE International Symposium on Multimedia (ISM 2006), 2006

2005

Low Complexity Programmable Cellular Automata Based Reconfigurable General Modular Mutiplier in GF(2m).

I. J. Comput. Appl., 2005

An Efficient Authentication Scheme with Fault Tolerance for Database Systems.

Proceedings of the Third International Conference on Information Technology and Applications (ICITA 2005), 2005

A Privacy Enhanced Role-Based Access Control Model for Enterprises.

Proceedings of the Networking and Mobile Computing, Third International Conference, 2005

2004

An XML-Based Administration Method on Role-Based Access Control in Distributed Systems.

I. J. Comput. Appl., 2004

A systematic approach for encryption and authentication with fault tolerance.

Computer Networks, 2004

A Cellular Automata Based Reconfigurable Architecture for Hybrid Cryptosystems.

Comput. J., 2004

An Integrated Approach for Database Security and Fault Tolerance.

Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

An Efficient Group Key Management Scheme for Secure Multicast with Multimedia Applications.

Proceedings of the Public Key Infrastructure, 2004

Using Metadata to Protect the Audiovisual Contents in MPEG-7 Applications.

Proceedings of the International Conference on Security and Management, 2004

2003

Integrating Object Oriented Role-Based Access Control Model with Mandatory Access Control Principles.

JCIS, 2003

An XML-based administration method on role-based access control in the enterprise environment.

Inf. Manag. Comput. Security, 2003

Design of Reconfigurable VLSI Architecture for Hybrid Arithmetic in $GF(2^m)$.

Comput. J., 2003

Designing Secure E-Commerce with Role-based Access Control.

Proceedings of the 2003 IEEE International Conference on Electronic Commerce (CEC 2003), 2003

An Approach to Secure Information Flow on Object Oriented Role-based Access Control Model.

Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

An XML Based Administration Method on Role-Based Access Control in the Enterprise Environment.

Proceedings of the ICEIS 2003, 2003

Secure Web-based Applications with XML and RBAC.

Proceedings of the IEEE Systems, 2003

2002

Designing a Complete Model of Role-based Access Control System for Distributed Networks.

J. Inf. Sci. Eng., 2002

Efficient Cellular Automata Based Versatile Multiplier for GF(2m).

J. Inf. Sci. Eng., 2002

A hybrid approach of wavelet packet and directional decomposition for image compression.

Int. J. Imaging Systems and Technology, 2002

Information flow analysis on role-based access control model.

Inf. Manag. Comput. Security, 2002

A DSP Based POD Implementation for High Speed Multimedia Communications.

EURASIP J. Adv. Sig. Proc., 2002

Low-Complexity Versatile Finite Field Multiplier in Normal Basis.

EURASIP J. Adv. Sig. Proc., 2002

2001

An Object-Oriented RBAC Model for Distributed System.

Proceedings of the 2001 Working IEEE / IFIP Conference on Software Architecture (WICSA 2001), 2001

A DSP Based POD Implementation for High Speed Multimedia Communication.

Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, 2001

2000

Logic operations based on single neuron rational model.

IEEE Trans. Neural Netw. Learning Syst., 2000

DCSA Systolic Array for Modular Multiplication and RSA Encryption.

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Some Space Considerations of VLSI Systolic Array Mappings.

Proceedings of the Seventh International Conference on Parallel and Distributed Systems, 2000

1999

Single Neuron Rational Model of Arithmetic and Logic Operations.

Connect. Sci., 1999

A VLSI Programmable Cellular Automata Array for Multiplication in GF (2

^{n}).
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

1998

Two Improved Algorithms and Hardware Implementations for Key Distribution Using Extended Programmable Cellular Automata.

Proceedings of the 14th Annual Computer Security Applications Conference (ACSAC 1998), 1998

1996

A Generalized Square-Multiply Algorithm and VLSI Array Implementation for RSA.

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

Some Space Considerations of Space-Time Mappings into Systolic Array.

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

1995

Residue Systolic Implementations for Neural Networks.

Neural Computing and Applications, 1995

1994

Determining objective functions in systolic array designs.

IEEE Trans. VLSI Syst., 1994

An Optimal Fault-Tolerant Design Approach for Array Processors.

Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994

1993

A Systematic Approach for Designing Concurrent Error-Detecting Systolic Arrays Using Redundancy.

Parallel Computing, 1993

An Efficient Algorithm and Parallel Implementations for Binary and Residue Number Systems.

J. Symb. Comput., 1993

1992

Evaluation of a rational function.

Numerical Algorithms, 1992

A systematic approach for designing systolic arrays.

Proceedings of the Second Great Lakes Symposium on VLSI, 1992

1991

Mapping Multiple Problem Instances into a Single Systolic Array with Application to Concurrent Error Detection.

Proceedings of the International Conference on Parallel Processing, 1991

Designing VLSI systolic arrays with complex processing elements.

Proceedings of the First Great Lakes Symposium on VLSI, 1991

1987

Parallel Designs for Chinese Remainder Conversion.

Proceedings of the International Conference on Parallel Processing, 1987

Residue number conversion.

Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow, 1987

Computing multiple modulo summation (abstract only): a new algorithm, its VLSI designs and applications.

Proceedings of the 15th ACM Annual Conference on Computer Science, 1987

Formal verification of systolic networks using theorem proving techniques (abstract only).

Proceedings of the 15th ACM Annual Conference on Computer Science, 1987

1986

A fast carry-free algorithm and hardware design for extended integer GCD computation.

Proceedings of the SYMSAC 1986, 1986

1985

A Programmable Systolic Array for Arithmetic Operations in Galois Fields.

Proceedings of the International Conference on Parallel Processing, 1985

Binary paradigm and systolic array implementation for residue arithmetic.

Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

1984

Multi-Dimensional Systolic Networks for Discrete Fourier Transform.

Proceedings of the 11th Annual Symposium on Computer Architecture, 1984